Presentation is loading. Please wait.

Presentation is loading. Please wait.

10 July 2003Matthew Warren - Trigger Module Update1 CALICE ‘FEDROB’ BE-FPGA Trigger Module Update Matthew Warren University College London 10 July 2003.

Published byCleopatra Scott Modified over 9 years ago

Similar presentations

Presentation on theme: "10 July 2003Matthew Warren - Trigger Module Update1 CALICE ‘FEDROB’ BE-FPGA Trigger Module Update Matthew Warren University College London 10 July 2003."— Presentation transcript:

1 10 July 2003Matthew Warren - Trigger Module Update1 CALICE ‘FEDROB’ BE-FPGA Trigger Module Update Matthew Warren University College London 10 July 2003

2 Matthew Warren - Trigger Module Update2 Trigger Logic Block Diagram (v3 - 25/6/2003) 4x PreTrigger 1x BeamOn 4x Activity 1x Veto 8x Trigger Delayed Trig 1 Delayed Trig 8 ‘Sequencer and Sink’ Seq (8 bit) + Sink (24 bit) RAM = 32KByte RAM ‘Digitiser’ 32bit Shift Registers, Storage Registers (x9) Edge Detect Beam On Sync + Enable 6x Spare 1x Spare SEQ VME Veto Sync + Enable Pre-Trigger Sync + Enables Internal Trig Osc + Random + Timer Activity Sync + Enables 4x SR SEQ VME 4x SR SEQ VME SR VME Trigger Window + Timer VME IRQ SEQ VME Width/ Delay Trigger Sync IRQ SINK VME Trigger Enable, Latch, Shaper, Veto START STOP START STOP J2 EXT NIM 16 In J0 LVDS 5 In VME J0 LVDS 2 Out 1x Trigger 1x Clock 3x Spare J2 BP LVDS 8 Out EXT NIM 16 Out 4x Trigger 1x Clock VME 8 x Counter Delays (16 bit) Clock Control BE FPGA - Trigger Module 4x Spare TTS_J0_READY

3 10 July 2003Matthew Warren - Trigger Module Update3 Trig skew test 0 All signal in Bank 6, fed from a common OR block.

4 10 July 2003Matthew Warren - Trigger Module Update4 Internal Schema... EN Trigs In delay in EN prog delay func SEL Trig Trig En On Trig En Off Trig En VME - Registers

5 10 July 2003Matthew Warren - Trigger Module Update5 More Thinking - Async Latency Tests – requirements/procedures? - Actual functionality - Delays – sub-clock period needs/possibilities? - Integration with main BE-FPGA code? - Interface with Data RAM for easy readout - Register List - Names?

6 10 July 2003Matthew Warren - Trigger Module Update6 Timeline Week Starting (Monday) : 14 July: UCL/HEP Stuff, CALICE Trigger Block Diag 21: Holiday 28: ATLAS (New TIM Arrives from manufacture/RAL) 4 Aug: ATLAS 11: ATLAS / CALICE – Async Trig test 18: CALICE – Main Functional Code 25: CALICE– ditto 1 Sept: CALICE– Integration with BE-FPGA 8: CALICE / ATLAS 15: ATLAS / As required 22: ATLAS / As required 29: As required …

Download ppt "10 July 2003Matthew Warren - Trigger Module Update1 CALICE ‘FEDROB’ BE-FPGA Trigger Module Update Matthew Warren University College London 10 July 2003."

Similar presentations

Clock and Control Status Matt Warren, on behalf of Martin Postranecky.

Clock and Control Status Matt Warren, on behalf of Martin Postranecky.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,

XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
New Corporate Identity Poster Design Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick, Richard Shaw, Dave Robinson.

New Corporate Identity Poster Design Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick, Richard Shaw, Dave Robinson.
New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.

New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.
01/11/2002SNS Software Final Design Review1 V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls.

01/11/2002SNS Software Final Design Review1 V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls.
Programmable Interval Timer

Programmable Interval Timer
On-Chip Processing for the Wave Union TDC Implemented in FPGA

On-Chip Processing for the Wave Union TDC Implemented in FPGA
Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.

Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
External Interrupt Module MTT48 13 - 1 EXTERNAL INTERRUPT REQUEST MODULE (IRQ)

External Interrupt Module MTT EXTERNAL INTERRUPT REQUEST MODULE (IRQ)
23 October 2003Matthew Warren - Trigger Module Update - RAL1 CALICE CIRC BE-FPGA Trigger Module Update Matthew Warren University College London 23 October.

23 October 2003Matthew Warren - Trigger Module Update - RAL1 CALICE CIRC BE-FPGA Trigger Module Update Matthew Warren University College London 23 October.
24 September 2002Paul Dauncey1 Trigger issues for the CALICE beam test Paul Dauncey Imperial College London, UK.

24 September 2002Paul Dauncey1 Trigger issues for the CALICE beam test Paul Dauncey Imperial College London, UK.
28 February 2003Paul Dauncey - HCAL Readout1 HCAL Readout and DAQ using the ECAL Readout Boards Paul Dauncey Imperial College London, UK.

28 February 2003Paul Dauncey - HCAL Readout1 HCAL Readout and DAQ using the ECAL Readout Boards Paul Dauncey Imperial College London, UK.
Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.

Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.
6 June 2002UK/HCAL common issues1 Paul Dauncey Imperial College Outline: UK commitments Trigger issues DAQ issues Readout electronics issues Many more.

6 June 2002UK/HCAL common issues1 Paul Dauncey Imperial College Outline: UK commitments Trigger issues DAQ issues Readout electronics issues Many more.
Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique.

Calice ECAL Readout Hardware Status report Adam Baird ECAL Meeting 26 Sept 2003 LLR-Ecole Polytechnique.
MICE Workshop Sept 2004 AFEII for MICE Recall: AFEs mount on ether side of the VLPC cass, with fibers going to the VLPCs between them. AFE has 8 identical.

MICE Workshop Sept 2004 AFEII for MICE Recall: AFEs mount on ether side of the VLPC cass, with fibers going to the VLPCs between them. AFE has 8 identical.
CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic: Internal Organization of an FPGA José Nelson Amaral.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic: Internal Organization of an FPGA José Nelson Amaral.
29 January 2004Paul Dauncey - CALICE DAQ1 UK ECAL Hardware Status David Ward (for Paul Dauncey)

29 January 2004Paul Dauncey - CALICE DAQ1 UK ECAL Hardware Status David Ward (for Paul Dauncey)
David Nelson STAVE Test Electronics July 1, 2008 1 ATLAS STAVE Test Electronics Preliminary V3 Presented by David Nelson.

David Nelson STAVE Test Electronics July 1, ATLAS STAVE Test Electronics Preliminary V3 Presented by David Nelson.

Similar presentations

Ads by Google