1. OCRP RF Control WINLAB – Rutgers University Date : June 9 2010 Authors : Prasanthi Maddala, prasanthi.m@gmail.comprasanthi.m@gmail.com Khanh Le, kle@winlab.rutgers.edukle@winlab.rutgers.edu

2. SPI – Serial Peripheral Interface Synchronous serial data link standard. Operates in master/slave mode. SPI specifies 4 logic signals SCLK — Serial Clock (output from master) MOSI/SIMO — Master Output, Slave Input (output from master) MISO/SOMI — Master Input, Slave Output (output from slave) SS — Slave Select (active low; output from master) Some SPI slave devices do not have a data output port (No MISO) and a few devices use a bidirectional data port (MOSI/MISO). Data Transmission - Master configures the clock; uses a frequency < max. freq supported by the slave - Pulls the slave select low - During each clock cycle the Master sends a bit on MOSI and slave sends a bit on MISO – not all transmissions result in meaningful rd/wr s. Clock polarity and phase - In addition to setting the clock frequency, the master must also configure the clock polarity(cpol) and phase(cpha) with respect to the data.

3. SPI (contd.) At CPOL=0 base value of the clock is zero  For CPHA=0 (first edge), data is read on the clock's rising edge and data is changed on a falling edge  For CPHA=1 (second edge), data is read on the clock's falling edge and data is changed on a rising edge. At CPOL=1 the base value of the clock is one (inversion of CPOL=0)  For CPHA=0, data is read on clock's falling edge and data is changed on a rising edge.  For CPHA=1, data is read on clock's rising edge and data is changed on a falling edge. This timing applies to both the master and the slave device.

4. SDR Platform V1.1 (Dual RF)

5. SPI Devices on SDR V1.1 DeviceNo. on WDR Comm. Cycle width Type of SPI AD9862 (ADC/DAC on DiBo) 216 or 244-wire. Allows 2 word write. MSB(dflt) or LSB first. Max sclk- 16 MHz. Data read on rising edge, clocked out on falling edge. MAX2829 (RF Transceiver on WiBo) 2183-wire, MSB first. No read. Max sclk-40 MHz(?). Data read on rising edge. MM74HC595 (U2- RF Control Register on WiBo) 28Can be thought of as a 3-wire SPI device with sclk connected to the shift register clock and cs connected to the storage register clock. Data read on rising edge. Antenna Switches are controlled from the common RMAP directly just like the LEDs – they don’t go through the RF control block

6. RF Control (SDR)

7. RF Control – Control RMAP Interface Signal NameIn/OutWidthDescription i_rfctl_wr_dataIn40Data to be sent to the SPI device serially – MSB first i_spi_cycle_lenIn6Length of the SPI communication cycle - Ex: length of valid write data for an SPI wr cycle. i_selIn4SPI device code i_enIn1Rising edge on this signal indicates a request for start of SPI transmission i_modeIn2SPI mode – cpol&cpha i_freq_divIn4Freq. of sclk = Freq. of i_clk / (2 ^ i_freq_div) i_stall_startIn6No.of sclk cycles after which sclk has to be stalled. 0 – no clock stalling i_stall_stopIn6No.of sclk cycles after which sclk comes out of stall mode and runs normally. o_rfctl_rd_dataOut32Data read from the SPI device during an SPI communication cycle. o_doneOut1Rising edge on this signal indicates the completion of an SPI communication cycle.

8. Signal NameIn/OutWidthDescription i_start_txIn1Rising edge on this signal is a request for start of transmission (an SPI communication cycle) i_wr_dataInMAX_CYCLE_WIDTH (RF Control Generic ) Data to be clocked out serially (MSB first) i_cycle_lenIn6Length of the communication cycle – size of rd/wr data i_stall_startIn6No.of sclk cycles after which sclk has to be stalled. 0 – no clock stalling i_stall_stopIn6No.of sclk cycles after which sclk comes out of stall mode and runs normally. i_freq_divIn4Freq. of sclk = Freq. of i_clk / (2 ^ i_freq_div) i_modeIn2Spi mode – cpol&cpha o_rd_dataOutMAX_CYCLE_WIDTH (RF Control Generic ) Data read from the SPI device during a communication cycle o_tx_doneOut1Rising edge on this signal indicates the end of a communication cycle, acts a sync pulse for o_rd_data. Generic SPI – SPI Control Interface

9. AD9862 64 registers, 8 bit wide. 16/24 bit rd/wr cycle - registers are updated on 16 th or 24 th rising clock edge. Incomplete operations are ignored Writing to a register rmap_cmd(wr, spi_wr_reg_0, 00(rd/wr & 2/1)&addr(6 bits)&data(8 bits)) -- data(16) for 2 word write rmap_cmd(wr, spi_ctl_reg, length(16)&device(AD9862(1/2)&en(1)) --- ***** bit locations are not accurate rmap_cmd(wr, spi_ctl_reg, length(16)&device(AD9862(1/2))&en(0)) Reading from a register rmap_cmd(wr, spi_wr_reg_0, 10&addr(6)&dummydata(8)) -- data(16) for 2 word rd rmap_cmd(wr, spi_ctl_reg, length(16)&device(AD9862(1/2)&en(1)) rmap_cmd(wr, spi_ctl_reg, length(16)&device(AD9862(1/2))&en(0)) rmap_cmd(rd, spi_rd_reg) - spi_rd_reg(7:0) will contain the required data

10. MAX2829 13 registers, 14 bit wide. 18 bit wr cycle – less than 18 bits are allowed. Frame starts with nCS going low and ends with nCS going high. Last 18 bits that are shifted in are latched with the rising edge of nCS. Bits are shifted in MSB first, on rising edge of sclk when nCS is low. Writing to a register rmap_cmd(wr, spi_wr_reg_0, data(14)&addr(4)) rmap_cmd(wr, spi_ctl_reg, length(18)&device(MAX2829(Tx/Rx)&en(1)) ***** bit locations are not accurate rmap_cmd(wr, spi_ctl_reg, length(18)&device(MAX2829(Tx/Rx))&en(0)) wait_for_intr();