1. 4 - 1 Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH) Module 4 : Interrupt System C28x 32-Bit-Digital Signal Controller TMS320F2812

2. 4 - 2 C28x Core Interrupt Lines C28xCORE  2 non-maskable interrupts (RS, “selectable” NMI)  14 maskable interrupts (INT1 – INT14) INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 RS NMI

3. 4 - 3 C28x Reset Sources Watchdog Timer RS pin active To RS pin RS C28x Core

4. 4 - 4 Register Bits Initialized at Reset Register bits defined by reset PC0x3F FFC0PC loaded with reset vector ACC0x0000 0000Accumulator cleared XAR0 - XAR7 0x0000 0000Auxiliary Registers DP0x0000Data Page pointer points to page 0 P0x0000 0000P register cleared XT0x0000 0000XT register cleared SP0x0400Stack Pointer to address 0400 RPC0x00 0000Return Program Counter cleared IFR0x0000no pending interrupts IER0x0000maskable interrupts disabled DBGIER0x0000debug interrupts disabled

5. 4 - 5 Control Bits Initialized at Reset Status Register 0 (ST0) SXM = 0Sign extension off OVM = 0Overflow mode off TC = 0test/control flag C = 0carry bit Z = 0zero flag Status Register 1 (ST1) INTM = 1Disable all maskable interrupts - global DBGM = 1Emulation access/events disabled PAGE0 = 0Stack addressing mode enabled/Direct addressing disabled VMAP = 1Interrupt vectors mapped to PM 0x3F FFC0 – 0x3F FFFF SPA = 0stack pointer even address alignment status bit LOOP = 0Loop instruction status bit EALLOW = 0emulation access enable bit IDLESTAT = 0Idle instruction status bit AMODE = 0C27x/C28x addressing mode OBJMODE = 0C27x object mode M0M1MAP = 1mapping mode bit XF = 0XF status bit ARP = 0ARP points to AR0 N = 0negative flag V = 0overflow bit PM = 000set to left-shift-by-1 OVC = 00 0000overflow counter

6. 4 - 6  A valid signal on a specific interrupt line causes the latch to display a “1” in the appropriate bit Maskable Interrupt Processing Conceptual Core Overview 1 0 1 (IFR) “Latch”INT1 INT2 INT14CoreInterruptC28xCore (INTM) “Global Switch” (IER) “Switch”  If the individual and global switches are turned “on” the interrupt reaches the core

7. 4 - 7 Interrupt Flag Register (IFR) RTOSINTDLOGINTINT14INT13INT12INT11INT10INT9 8 9 1011121314 15 INT8INT7INT6INT5INT4INT3INT2INT1 0 1234567 Pending :IFR Bit = 1 Absent :IFR Bit = 0  Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR  If interrupt occurs when writing IFR, interrupt has priority  IFR(bit) cleared when interrupt is acknowledged by CPU  Register cleared on reset /*** Manual setting/clearing IFR ***/ extern cregister volatile unsigned int IFR; IFR |= 0x0008;//set INT4 in IFR IFR |= 0x0008;//set INT4 in IFR IFR &= 0xFFF7;//clear INT4 in IFR IFR &= 0xFFF7;//clear INT4 in IFR

8. 4 - 8 Interrupt Enable Register (IER) RTOSINTDLOGINTINT14INT13INT12INT11INT10INT9 8 9 1011121314 15 INT8INT7INT6INT5INT4INT3INT2INT1 0 1234567 Enable: Set IER Bit = 1 Disable: Clear IER Bit = 0  Compiler generates atomic instructions (non-interruptible) for setting/clearing IER  Register cleared on reset /*** Interrupt Enable Register ***/ extern cregister volatile unsigned int IER; IER |= 0x0008;//enable INT4 in IER IER |= 0x0008;//enable INT4 in IER IER &= 0xFFF7;//disable INT4 in IER IER &= 0xFFF7;//disable INT4 in IER

9. 4 - 9 Interrupt Global Mask Bit  INTM used to globally enable/disable interrupts:  Enable:INTM = 0  Disable:INTM = 1 (reset value)  INTM modified from assembly code only: INTM ST1 Bit 0 Bit 0 /*** Global Interrupts ***/ asm(“ CLRC INTM”); //enable global interrupts asm(“ CLRC INTM”); //enable global interrupts asm(“ SETC INTM”); //disable global interrupts asm(“ SETC INTM”); //disable global interrupts

10. 4 - 10 Peripheral Interrupt Expansion - PIE Peripheral Interrupts 12x8 = 96 IFR IER INTM 28xCore 28x Core Interrupt logic PIE module for 96 Interrupts INT1.x interrupt group INT2.x interrupt group INT3.x interrupt group INT4.x interrupt group INT5.x interrupt group INT6.x interrupt group INT7.x interrupt group INT8.x interrupt group INT9.x interrupt group INT10.x interrupt group INT11.x interrupt group INT12.x interrupt group INT1 – INT 12 12 Interrupts 96 INT1.1 INT1.2 INT1.8 1 0 1 INT1 PIEIFR1PIEIER1 Interrupt Group 1 INT13 INT13 (TINT1 / XINT13) INT14 INT14 (TINT2) NMI

11. 4 - 11 PIE Registers INTx.2INTx.3INTx.4INTx.5INTx.6INTx.7INTx.8INTx.1 01234567 15 - 8 reserved PIEIFRx register (x = 1 to 12) INTx.2INTx.3INTx.4INTx.5INTx.6INTx.7INTx.8INTx.1 01234567 15 - 8 reserved PIEIERx register (x = 1 to 12) reserved PIEACKx PIE Interrupt Acknowledge Register (PIEACK) 12435678901011 15 - 12 ENPIE PIEVECT PIECTRL register 0 15 - 1 #include “DSP28_Device.h” PieCtrlRegs.PIEIFR1.bit.INTx4 = 1; //manually set IFR for XINT1 in PIE group 1 PieCtrlRegs.PIEIER3.bit.INTx5 = 1; //enable CAPINT1 in PIE group 3 PieCtrlRegs.PIEACK.all = 0x0004; //acknowledge the PIE group 3 PieCtrlRegs.PIECTRL.bit.ENPIE = 1; //enable the PIE

12. 4 - 12 F2812/10 PIE Interrupt Assignment Table INTx.8INTx.7INTx.6INTx.5INTx.4INTx.3INTx.2INTx.1 INT1WAKEINTTINT0ADCINTXINT2XINT1PDPINTBPDPINTA INT2T1OFINTT1UFINTT1CINTT1PINTCMP3INTCMP2INTCMP1INT INT3CAPINT3CAPINT2CAPINT1T2OFINTT2UFINTT2CINTT2PINT INT4T3OFINTT3UFINTT3CINTT3PINTCMP6INTCMP5INTCMP4INT INT5CAPINT6CAPINT5CAPINT4T4OFINTT4UFINTT4CINTT4PINT INT6MXINTMRINTSPITXINTASPIRXINTA INT7 INT8 INT9SCITXINTBSCIRXINTBSCITXINTASCIRXINTA INT10 INT11 INT12 ECAN0INTECAN1INT

13. 4 - 13 Interrupt Response - Hardware Sequence Note: some actions occur simultaneously, none are interruptible CPU ActionDescription TST0 AHAL PHPL AR1AR0 DPST1 DBSTATIER PC(msw)PC(lsw) Registers  stack14 Register words auto saved 0  IFR (bit)Clear corresponding IFR bit 0  IFR (bit)Clear corresponding IFR bit 0  IER (bit)Clear corresponding IER bit 0  IER (bit)Clear corresponding IER bit 1  INTM/DBGMDisable global ints/debug events 1  INTM/DBGMDisable global ints/debug events Vector  PCLoads PC with int vector address Vector  PCLoads PC with int vector address Clear other status bitsClear LOOP, EALLOW, IDLESTAT Clear other status bitsClear LOOP, EALLOW, IDLESTAT

14. 4 - 14 C28x CPU Timers RESET Timer Reload SYSCLKOUT TCR.4 16 - Bit divide down TDDRH:TDDR 16 - Bit prescaler PSCH:PSC 32 - Bit period PRDH:PRD 32 - Bit counter TIMH:TIM BORROW INT

15. 4 - 15 C28x Timer Interrupt System IFR IER INTM 28xCore 28x Core Interrupt logic PIE unit INT1.7 interrupt INT1 TINT1 / XINT13 TINT1 / XINT13 TINT2 TINT0 INT13 INT14

16. 4 - 16 AddressRegisterName 0x0000 0C00TIMER0TIMTimer 0, Counter Register Low 0x0000 0C01TIMER0TIMHTimer 0, Counter Register High 0x0000 0C02TIMER0PRDTimer 0, Period Register Low 0x0000 0C03TIMER0PRDHTimer 0, Period Register High 0x0000 0C04TIMER0TCRTimer 0, Control Register 0x0000 0C06 TIMER0TPRTimer 0, Prescaler Register 0x0000 0C07 TIMER0TPRHTimer 0, Prescaler Register High 0x0000 0C08TIMER1TIMTimer 1, Counter Register Low 0x0000 0C09TIMER1TIMHTimer 1, Counter Register High 0x0000 0C0ATIMER1PRDTimer 1, Period Register Low 0x0000 0C0BTIMER1PRDHTimer 1, Period Register High 0x0000 0C0CTIMER1TCRTimer 1, Control Register 0x0000 0C0DTIMER1TPRTimer 1, Prescaler Register 0x0000 0C0FTIMER1TPRHTimer 1, Prescaler Register High 0x0000 0C10 to 0C17 Timer 2 Registers ; same layout as above C28x Timer Registers

17. 4 - 17 C28x Timer Control Registers TIMERxTCR Emulator Interaction 1x = run free 0 reservedTRB 1234567 reserved TSSreserved TIEreservedFREE 89101112131415 reservedSOFTreserved TIF Timer Stop Status 0 = start / 1 = stop Timer Reload Bit 1 = reload Timer Interrupt Flag Write 1 clear bit Timer Interrupt Enable Write 1 to enable INT