1. STMicroelectronics « Trends in high speed, low power Analog to Digital converters »  Laurent Dugoujon  Data-Converters Design Mgr.

2. LECC2002 9-13 September 2002, Colmar-France Outline Introduction/Generalities ADC challenges ST ADC products Power Optimisation Design views ADC Trends Conclusion

3. STMicroelectronics Introduction/Generalities  DEFINITIONS

4. LECC2002 9-13 September 2002, Colmar-France Analog to Digital Converter (ADC) ANALOG INPUT D0 D3 D2 D1 DIGITAL OUTPUT Ex:4 bits A/D converter. t analog input Sampling Clock signal TSA04XX 010010111… 1 1 1 16 possible output codes ADC Full scale amplitude LSB=Full scale/2 N 62mV for 1V/4bits

5. LECC2002 9-13 September 2002, Colmar-France ADC MAIN PARAMETERS ADC functionality parameters: – Number of output bits – Sampling frequency noted F S – Number of channels ADC performance parameters: – Static parameters: DNL, INL – Dynamic parameters: SNR, SINAD, ENOB, Analog input bandwidth. – Power consumption, Area, Package

6. STMicroelectronics Generalities  ADC Market, Applications

7. LECC2002 9-13 September 2002, Colmar-France ADC Market Source:WSTS ADC, DAC, SWITCHES & MUX Regions US 42% Europe 22% Japan 18% A/P 16% Year 2000 – 1.8B$ total value – 646Mu total volume

8. LECC2002 9-13 September 2002, Colmar-France High Energy Physics Electronic chain Detector ADC PA Data Processor DAQ DCS Sensor Signal formating Events acquisition Storage Control Analysis…

9. LECC2002 9-13 September 2002, Colmar-France Hi-volumes & Hi-tech Applications Consumer Audio Industrial Control Consumer Video RF/Military Sampling Frequency Nbr. bits HEP HEP Detectors requirements 10 10MHz + low Power + no. channels AP Astro-Physics Telecom

10. STMicroelectronics ADC Challenge  ACCURACY and SPEED?

11. LECC2002 9-13 September 2002, Colmar-France Speed-Accuracy coupling Fundamental relation (Heisenberg):  m h/2.   LSB    R  Applied to A/D Converter: R=50 Ohms, 2 N.LSB = 1Volt, h=6.626 10 -34 2 N.Fsamp <= 3.44 10 15 ex: 12 bits/840Gsamples/s Or 18bits/10Gsamples/s T/2 LSB/2 Vin Time

12. LECC2002 9-13 September 2002, Colmar-France Real signals world How many Gigabit/s on a wire ? Today commercial 10Gbit/s with ECL levels Power, EMI, Integrity loss, Package parasitics,.. Are the limiting factors against higher rates !

13. LECC2002 9-13 September 2002, Colmar-France Clock accuracy problems Generation of Clock signal: Clock signal is usually the fastest signal of the acquisition system and determines the sampling instants: signal clock jitter

14. LECC2002 9-13 September 2002, Colmar-France Low-jitter Clock generation Clock jitter: It characterizes the Quality of the time reference, often expressed in ps pk-to-pk or rms. Available generator technologies: RC + LogicXtal, VCXOSp. Plls Jitter100-1000ps10-100ps0.5-10ps Cost~0.1$~1$~10$

15. LECC2002 9-13 September 2002, Colmar-France Clock Quality vs ADC specs Aperture time and Clock jitter for a Nbit ADC sampling an Analog signal of FIN frequency must be less than: 1/(PI x FIN x 2 (N+1) ) In order not to add degradation in the achieved Signal/Noise Ratio. Example: 10 bit conversion of 10MHz input needs less than 16ps jitter. (good quality Xtal oscillator is OK) 12bit of same 10MHz input needs 4ps max jitter !

16. LECC2002 9-13 September 2002, Colmar-France Accuracy/speed 2 4 6 8 10 14 12 16 18 20 22 0 10K100K1M10M100M1G10G100G Heisenberg 1ps jitter Effect. bits Sample rate S/s

17. LECC2002 9-13 September 2002, Colmar-France Sampling rate trend summary Today best system clock jitter is 1ps Corresponding to 12bit resolution of 40MHz input signal Prototypes ADCs reach 0.5ps aperture time (8bit/1.3GHz) Going beyond 12bit-40MHz will require sub-ps jitter clock generator preferably integrated to the ADC chip for noise, power and cost reductions.

18. LECC2002 9-13 September 2002, Colmar-France Resolution of real conversion systems is limited by the « noise floor » resulting from differents noise sources: thermal noise, transistors intrinsic noise, … Input-referred noise can be expressed as: = 4 kTR eq F s /2 This should be less than Quantization noise that is: Q 2 /12, Q=Full scale/2 N Then : N < Log 2 {Vfs 2 /(6kTR eq Fs)} 1/2 – 1 Given a 2Volts full scale and 1000ohms Req, it gives 19bit sampling at 100Ksps (or 16bit at 10Msps) Resolution Problems Rnoise Equiv. Noiseless ADC R eq Vin

19. LECC2002 9-13 September 2002, Colmar-France Accuracy/speed 2 4 6 8 10 14 12 16 18 20 22 0 10K100K1M10M100M1G10G100G Heisenberg 1Kohm thermal 1ps jitter Effect. bits Sample rate S/s

20. LECC2002 9-13 September 2002, Colmar-France High-speed ADCs ST products & services TSA0801: 8-bit, single-Channel, 40Msps, 40mW TSA1001: 10-bit, single-Channel, 25Msps, 35mW TSA1002: 10-bit, single-Channel, 50Msps, 50mW TSA1201: 12-bit, single-Channel, 50Msps, 130mW TSA1203: 12-bit, dual-Channel, 40Msps, 230mW TSA1204: 12-bit, dual-Channel, 20Msps, 120mW TSA1005: 10-bits, dual Channel, 40 Msps, 200mW 2.5V supply voltage TQFP48 + Evaluation boards, Applications notes, support, IP integration, consulting…

21. LECC2002 9-13 September 2002, Colmar-France ST ADCs Accuracy/speed 2 4 6 8 10 14 12 16 18 20 22 0 10K100K1M10M100M1G10G100G Heisenberg 1Kohm thermal 1ps jitter Effect. bits Sample rate S/s products prototypes

22. LECC2002 9-13 September 2002, Colmar-France Power optimisation MeritFig.=2 ENOB x F s / Power ( x 10 -11 ) TSA1001 9.7b, 25Msps 35mW MF=5.9 Closest competitor MF=3.2 TSA1002 9.7b, 50Msps 50mW MF=8.3 Closest competitor MF=4.2 TSA1201 10.5b, 50Msps 130mW MF=5.6 Closest competitor MF=4.7 TSA1203 (dual) 10.5b, 40Msps 230mW MF=5 Closest competitor MF=2 Closest competitor MF=1.2 TSA0801 7.9b, 40Msps 40mW MF=2.4 ADCs V supply =2.5V Competitors V supply = 5V or 3.3V…

23. LECC2002 9-13 September 2002, Colmar-France Design architectures

24. LECC2002 9-13 September 2002, Colmar-France Very High Speed ADC (8bits/2Gsps) Interleaved SAR ADCs SA ADC 1 SA ADC 24 SA ADC 13 SA ADC 12 V IN 8 8 8 8 MUX 12:1 8 MUX 12:1 8 COMP DAC S/H Die: 4mm 2, IP: 0.45mm 2 24 // unitary SAR ADC 0.18  m CMOS

25. LECC2002 9-13 September 2002, Colmar-France Pipelined ADCs S/H 2bit x2 Vi-1Vi Digital correction Output bits 1 pipeline stage

26. LECC2002 9-13 September 2002, Colmar-France Folded-cascode Amplifier pol inpinm op om vcp vcn VDD GND Vtp=Vtn=0.7V 2.5V / 0.25  m CMOS G=90dB THD=-86dB BW 3dB =100MHz

27. LECC2002 9-13 September 2002, Colmar-France CERN Alice-TPC ALTRO chip

28. LECC2002 9-13 September 2002, Colmar-France 7.7 mm 8.3 mm Data Memory 1K x 40 Pedestal Memory 1K x 10 Processing Logic 3.8 mm 12 mm 14.1 mm TQFP 176 24mm CERN ALTRO chip: Layout and Package

29. LECC2002 9-13 September 2002, Colmar-France CERN ALTRO ADC results MAX sampling rate in the TPC BW at PASA output TPC requirement: ENOB > 9 2.5 kk kk kk kk

30. LECC2002 9-13 September 2002, Colmar-France 90 k  12 mW 9.7 ADC Operating Point Effective Number of Bits Power Consumption per Channel ADC Power Consumption 20 k  30 mW MPW values Engineering Run values Measured Analogue Power Consumption: 80 mA (st.dev = 1.12 mA) 12.5 mW / channel Optimised ADC power in ALTRO

31. LECC2002 9-13 September 2002, Colmar-France CERN ALTRO spectrum analysis Without Readout ClockWith Readout Clock HD2HD3 HD2 HD3 RDO clock HD4

32. LECC2002 9-13 September 2002, Colmar-France INPUT SIGNALAFTER 1 st BASELINE CORRECTION AFTER TAIL CANCELLATIONAFTER 2 nd BASELINE CORRECTION ALTRO chip: Digital Processor Performance

33. LECC2002 9-13 September 2002, Colmar-France ADC Trends Resolution-Speed Paralelism to exploit technology intrinsic speed of successive generations technology (X2 every 2years) Intensification of integrated Digital Post-processing Number of channels Lower core sizes and power will allow higher integration Associated Functions Internal Clock re-generation will appear, Built-In-Self-Test,… Power New low-voltage cells/architectures for 1V technology on the way… Packages Parasitics and size reduction associated to better dissipation

34. LECC2002 9-13 September 2002, Colmar-France Conclusions ADCs are used in many applications HEP is not so specific in terms of need Application Environment can degrades ADC perf. High Merit-figure ADC design needs large efforts Multi-ADCs integration is a powerfull path Digital integration is the same natural path We will use Moore’s law to buy resolution.speed