1. CRKIT R5 Clock Architecture
WINLAB – Rutgers University
June 13, 2013
Khanh Le

2. Zedboard Zynq System Clock Overview
4 programmable
PL clocks
E19, E20
dac_clk_out (dac source synchronous clock) PS PL
L18, L19
dac_clk_in (dac ref clock)
33.333MHz
ref clock
(IC18, PS_CLK) F7
B19, B20
ref_clk_out (RF ref clock ~30MHz)
D18, C19
adc_clk_in (adc source synchronous clock) Y9
For portability, use the 100MHz reference clock for PL section
(will require one PLL)
100MHz
ref clock
(IC17, GCLK)

3. Zynq PS System Clocks Check the clocks on EDK tool !! (REVISIT)
Ratio
Generator
cpu_6x4x
CPU, SCU
OCM
ARM PLL
cpu_3x2x
Mux
6-bit prog.
divider
Sync
cpu_2x
AXI
Interconnect
33.333MHz
PS_CLK
I/O PLL
cpu_1x
DDR PLL
6-bit prog.
divider
ddr_3x
Async
6-bit prog.
divider
ddr_2x
Async
Check the clocks
on EDK tool !!
(REVISIT)
I/O Peripherals
USB, Ethernet
SDIO, SMC
Mux
6-bit prog.
divider
SPI, QSPI, UART
CAN, I2C PL
PL Clocks

4. RF Interface Tx Baseband Rx Baseband AD9122 DAC AD9523 Clock Gen
REVISIT : do we need interpolation in the framework ? Or use the DAC for interpolation ?
Answer – interpolation within Framework.
(Up/Down conversion not critical at this point)
By default,
+Rising edge = I
+Falling edge = Q
+Twos complement
ODDR
(SAME_EDGE Mode) Tx
Baseband
LVDS
Sampling Rate
Up Conversion I D1
dac_data_out[15:0]
AD9122
DAC Q D2 Q
dac_clk_out 1 D1
dac_frame_out (unused) Q D2
Not used for word-level, only for
Byte- or Nibble-level
@prog_tx_clk
@tx_clk
NOT NEEDED
(no clock deskew)
clock feedback
dac_clk_in
AD9523
Clock Gen
CLKOUT1
CMT
PLL
Jitter clean up
CLKOUT0
DAC Interface
AD9548
Clock Sync
@100MHz
sys_clk
M=3, D=2, O0=1.5
ref_clk_out(~30MHz)
CLKOUT0
100MHz
CMT
MMCM
CTL REG
CLKOUT1
Programmable
ref. clock
(ug472)
M=3, D=2, O1=5
RF Reference Clock
By default,
+Rising edge = I
+Falling edge = Q
+Twos complement
+ ~1ns skew between data and DCO
(DCO delay vs data)
INT REG
IDDR
(SAME_EDGE_PIPELINED Mode) Rx
Baseband
Sampling Rate
Down Conversion
adc_data_in[13:0]
AD9643
ADC I Q1 Q Q2 D
adc_clk_in
Clock domain crossing. Must support fractional synchronization e.g. 125MHz -> 20MHz
@125MHz
adc_or_in
clock feedback
CLKOUT1
@prog_rx_clk
CMT
MMCM
CLKOUT0
Anti-aliasing filter
-> Nyquist sampling
For fractional clock divider
ADC Interface
@125MHz
PCORE
scl
I2C -> SPI
I2C Interface
sdata

5. ODDR Timing

6. IDDR Timing

7. DAC Timing DAC Register Map Default
Data bus sampling point is nominally 350ps after each edge of DCI signal,
with uncertainty of +/- 300 ps.
Data interface timing can be verified using the
Sample Error Detection (SED) circuitry (reg 0x07, 0x67-0x73).
Default
DAC Register Map
Reference : AD9122_DAC.pdf

8. ADC Timing ADC Register Map Interleaved IQ channels : Chan A = I
~1ns skew between data and DCO
Interleaved IQ channels :
Chan A = I
Chan B = Q
ADC Register Map
Reference : AD9643_ADC.pdf
For parallel interleaved mode

9. Xilinx 7-series Clock Management Tile (CMT)
Phased-lock loop, subset of
MMCM functions
Recovered clock
From Deserialiser
Applications :
+ clock network deskew
+ frequency synthesis
+ jitter reduction
Mixed-mode clock manager
1 CMT = 1 MMCM + 1 PLL
Zynq Z-7020 PL clock resources :
+ 4 CMTs e.g. 4 MMCMs & 4 PLLs
+ 4 programmable clocks from PS

10. CMT - MMCM With Fclkin = 100MHz, M=1, D=1 : Integer divide :
Independent clock control
Integer
counter
Attributes :
M = CLKFBOUT_MULT_F
D = DIVCLK_DIVIDE
O = CLKOUT_DIVIDE
(ug472, page 79)
Fractional
counter
With Fclkin = 100MHz, M=1, D=1 :
Integer divide :
O0 = 1 : Fout = 100MHz
O1 = 2 : Fout = 50MHz
O2 = 3 : Fout = 33.33MHz
O3 = 4 : Fout = 25MHz
O4 = 5 : Fout = 20MHz
O5 = 6 : Fout = 16.66MHz
Fout = 80MHz, then O0 = Fclkin/Fout = 100/80 = 10/8 = 1.25 (fractional divide).
Fout = 30MHz, O0 = 100/30 = …
Alternative,
M=3, D=2, O1=5 : CLKOUT1 = 30MHz (rf ref clock)
M=3, D=2, O0=1.5 : CLKOUT0 = 100MHz (system clock)
Programming port
(ug xapp888)
With Fclkin = 125MHz (ADC sync clock), M=1, D=1 :
Fout = 80MHz, O0 = 125/80 =
Fout = 20MHz, O0 = 125/20 = 6.25

11. CMT - PLL Integer only counter Attributes : M = CLKFBOUT_MULT_F
D = DIVCLK_DIVIDE
O = CLKOUT_DIVIDE
Programming port

12. MMCM and PLL Use Models (ug472, page 87)
Requires two BUFGs
Requires only one BUFG
+ jitter filtering
+ frequency synthesis
+ no phase requirement between Fin and Fout
Input buffers must
be in same bank.
Use COREGEN to get additional settings information.
Off-chip compensation

13. Clock Network Deskew Restrictions1
Fin
Fout 2
FFB
Restrictions for feedback : 6
Example 1 :
Fin = 166MHz, D = 1, M = 6, O = 2
FVCO = M x FFB = M x (FIN / D)
FVCO = 6 x 166MHz = 996MHz
and
FOUT = FVCO / O = 996MHz / 2 = 498 MHz 2
Fin
Fout 4
FFB
Example 2 :
Fin = 66.66MHz, D = 2, M = 30, O = 4
FVCO = M x FFB = M x (FIN / D) = 30 x (66.66MHz / 2) = 999.9MHz ~ 1000MHz
and
FOUT = FVCO / O = 1000MHz / 4 = 250 MHz 30

14. ADC Network Deskew Example 1 : Given Fin = 125MHz,?
Fin ?
Fout0 -> rcv baseband clock
FFB ?
Fout1 -> adc interface clock e.g. decimation…
Example 1 :
Given Fin = 125MHz,
wants FOUT0 = 20MHz, FOUT1 = 125MHz
What are the appropriate values for D, M, O0 and O1 ?
(note, O0 = fraction, O1 = integer)
FOUT0 = FVCO / O0 = 20MHz -> O0 = FVCO / FOUT0
FOUT1 = FVCO / O1 = 125MHz -> O1 = FVCO / FOUT1
FVCO ?
FVCO = M x FFB = M x (FIN / D)
+Assuming D = 1, M = 2
=> FVCO = 2 x FIN = 2 x 125 = 250 MHz
And
O0 = FVCO / FOUT0 = 250 / 20 = 12.5
O1 = FVCO / FOUT1 = 250 / 125 = 2
+Assuming D = 1, M = 4
=> FVCO = 4 x FIN = 4 x 125 = 500 MHz
O0 = FVCO / FOUT0 = 500 / 20 = 25
O1 = FVCO / FOUT1 = 500 / 125 = 4 ?
Restrictions for feedback :
Example 2 :
Given Fin = 125MHz,
wants FOUT0 = 80MHz, FOUT1 = 125MHz
+Assuming D = 1, M = 2
=> FVCO = 2 x FIN = 2 x 125 = 250 MHz
And,
O0 = FVCO / FOUT0 = 250 / 80 = 3.125
O1 = FVCO / FOUT1 = 250 / 125 = 2
+Assuming D = 1, M = 4 (doubles)
=> FVCO = 2 x FIN = 4 x 125 = 500 MHz
O0 = FVCO / FOUT0 = 500 / 80 = 6.25 (doubles)
O1 = FVCO / FOUT1 = 500 / 125 = 4 (doubles)

15. Interpolation/Decimation Rational Sampling Rate Converters
SAVE FOR LATER ! Not critical at this point for Spectrum Sensing APP.
However, requires running the FFT ! This will be an
Interesting challenge as the Spectrum Sensing APP will be
and data forwarded onto system clock domain.
(Reference : Orfanidis book.)

16. Clock Network for Zedboard Zynq How many APPs can be supported ?
Zynq platforms are mostly meant for Spectrum Sensing applications.
We will need :
1. 1 MMCM for RF reference clock & system clock
2. 1 MMCM for ADC clock deskew & spectrum sensing APP
3. (optional) 1 PLL for Transmit Baseband APP & rate conversion, maybe replaced by MMCM for
rational upconversion rate. However, at this point this is not critical. Items 1 and 2 are more important for spectrum sensing APP.
Zynq Z7020 has 4 CMTs = 4 MMCMs & 4 PLLs in total. This is sufficient to support our spectrum sensing APP.

17. Clock Domain Abstraction Layers
Dynamic clock,
@125MHz or less
@100MHz
@100MHz
@100MHz
Clock domain crossing included in AXI bus
(revisit this)
@667MHz
Refer to separate document for further details.

18. Clock Dynamic Reconfiguration
Not critical for Spectrum Sensing APP running at However, will require clock dynamic reconfiguration at latter stages. Refer to Xilinx application note XAPP888 for further details and reference design.