1. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University Experiment on digital system

2. Outline ■ NAND & NOR Introduction ■ NAND & NOR Implementation ■ Two-Level & Three-Level Implementation ■ INVERSE Functions ■ Example ■ Adder ■ Subtractor ■ LAB

3. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University NAND & NOR Introduction

4. NAND & NOR Introduction (1/2) ■ NAND / NOR ❑ Basic gates used in all IC digital logic families. ❑ Needs inversion from AND/OR/NOT into NAND/NOR. ■ Compare with AND/OR ❑ Digital circuits are frequently constructed with NAND/NOR rather than AND/OR gates. ❑ NAND and NOR gates are easier to fabricate with electronic components than AND/OR. ❑ Cheaper (lower cost) and faster (less delay).

5. NAND & NOR Introduction(2/2)

6. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University NAND & NOR Implementation

7. ■ AND, OR, NOT can be designed from NAND gates. ■ “AND-OR” diagram ❑ → “NAND-NAND”. ■ “OR-AND” diagram ❑ → “NOR-NOR”.

8. NAND Implementation ■ A “universal” gate ❑ any digital system can be implemented with it ■ AND, OR, NOT can be obtained from NAND gates NAND x y (xy)’ 0 0 1 0 1 1 1 0 1 1 1 0 One-input NAND x x’ 0 1 1 0 =

9. NOR Implementation ■ A universal gate ■ The dual of NAND ❑ All procedures/rules for NAND are dual of the corresponding procedures/rules for NOR ■ NOT OR AND implemented with NOR NOR x y (x+y)’ 0 0 1 0 1 0 1 0 0 1 1 0 One-input NOR x x’ 0 1 1 0

10. Two Graphic Symbols for NAND & NOR Gate ■ 2 equivalent graphic symbols for NAND & NOR gate

11. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University Two-Level & Three-Level Implementation

12. Two-Level Implementation with NAND ■ Boolean function in sum of products form (AND-OR) ■ DeMorgan’s theorem F = AB + CD = ((AB)’(CD)’)’ // 2-level NAND implementation ■ “AND-OR” diagram → “NAND-NAND” (all NAND diagram) (AB)’ (CD)’ = ((AB)’(CD)’)’ AB CD AB+CD =

13. Two-Level Implementation with NOR ■ Requirement ❑ the Boolean function in product of sums ■ map → combining 0’s → complementing ■ “OR-AND” diagram → all-NOR diagram “NOR-NOR” ■ Multilevel implementation – similar to the one for NAND

14. Two-Level Implementation Example Implement F(x,y,z)=Σ(1,2,3,4,5,7) with NAND gates 1. Simplify F(x,y,z) in sum of products by means of “map”. 2. Draw a NAND gate for each product term with at least 2 literals. 3. Draw a single NAND gate in the 2nd level with inputs coming from outputs of 1st level. 4. A term with a single literal requires an inverter in the 1st level. 3 2 4 1

15. Three-level Implementation Example: F = (AB′ +A′B)(C + D′) Implementing F = (AB′ +A′B)(C + D′) with NOR gates

16. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University INVERT Functions

17. AND-OR-INVERT Functions ■ AND-NOR = NAND-AND F = (AB+CD+E)’

18. OR-AND-INVERT Functions ■ OR-NAND = NOR-OR F = [(A+B)(C+D)E)]’

19. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University Example

20. A Three-Input Circuit (1/2) xyzxyz x y z O 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 input output truth table O O= x'yz + xy'z+ xyz' + xyz z x y 00 01 11 10 0101 1 1 1 1 z x y 00 01 11 10 0101 1 1 1 1 simplification O= xy + yz+ xz Good !!

21. A Three-Input Circuit (2/2) xyzxyz x y z O 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 input output truth table O z x y 00 01 11 10 0101 1 1 1 1 simplification O= xy + yz+ xz x z y xy yz xz o x z y o Low cost Less delay

22. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University Adder

23. Half adder (1/2) ■ Half adder (HA) ❑ Two inputs ■ Summand(a) 、 addend(b) ❑ Two outputs ■ Sum(S) 、 Carry(C) ■ Truth table abCS 0000 0101 1001 1110 a b+ SC

24. Half adder (2/2) S = a’b + ab’ = a b C = ab

25. Full adder (1/2) ■ A full adder is additionally designed with an input of carry. abcCS 00000 00101 01001 01110 10001 10110 11010 11111 Truth table

26. Full adder (2/2) ■ With two half adders and an OR gate. S = a’b’c + a’bc’ + ab’c’ + abc C = ab + ac + bc

27. Implementation of full adder ■ Sum of products S = a’b’c + a’bc’ + ab’c’ + abc C = ab + ac + bc

28. 2-Bit adder ■ With two full adders A1 B1+ A0 B0 C1 S0S1C2

29. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University Subtractor

30. Half subtractor ■ Half subtractor ❑ With two inputs: ■ minuend(a) 、 subtrahend (b) ❑ Two outputs: ■ Difference(d) 、 borrow(b)

31. Full subtractor ■ A full subtractor is designed with an additional input of borrow.

32. Digital Integrated Circuit Design Laboratory Department of Computer Science and Information Engineering National Cheng Kung University LAB

33. Lab ■ 2-Bit by 2-Bit Binary Multiplier ❑ Ex: 2x3 (10 x 11) ❑ B1=1, B0=0, A1=1, A0=1 ❑ =>A1B1=1, A1B0=0, A0B1=1, A0B0=0 Four input, B1,B0, A1,A0 Four output, C3, C2, C1, C0

34. Equipment NamesAmount Solerless Breadboard×1 74LS08×2 74LS86×1

35. 74LS08

36. 74LS86