1. Copyright © Am Road Electronics Co., Ltd. TMS320C24x Overview Max Chyou Engineering Manager AmRoad Co.Ltd. Maxchyou@amroad.com.tw

2. Contents Introduction Architectural Overview Clocks Power Management Interrupts Timer PWM Architecture Space Vector Q&A

3. Introduction

4. Introduction Why DSP? Benefits of Digital System  Reliability, flexibility  Time sharing / task switching  Freedom from environmental effects  Bandwidth and resolution of analog system

5. Introduction Why DSP? Optimized Architecture  Instruction set tailored for signal processing functions  Architecture minimizes numerical problems in processing discrete signals

6. Introduction Why DSP? High Performance  Implementation of complex algorithms in real-time  Implementation of high sampling rates  Minimizes computational delay  Performance to implement multiple functions

7. Introduction Features Features  Single-cycle instruction  DSP instruction set  Multiple buses  Hardware multiplier  Hardware scaling shifters Benefits Benefits  High sampling rates / control of high bandwidth system  Real-time execution of advanced control algorithms  Simultaneous access of data and instructions  Minimize computational delays

8. Introduction Features Features  Hardware scaling shifters  16-bit word length  32-bit ALU / ACC  Hardware stack  Saturation mode Benefits Benefits  Fast scaling / dynamic range  Minimize quantization errors  Minimize truncation errors  Fast interrupt processing  Prevent wrap around of ACC

9. Introduction Function Function  Notch filter algorithms  Adaptive Kalman filter algorithms  State estimator algorithms  Vector control algorithms  Pulse width modulation (PWM) Benefits Benefits  Cancel mechanical resonance  Reduce sensor noise  Estimate multiple variables  Real-time axis transformation  Improve motor control

10. Introduction Function Function  Notch filter algorithms  Adaptive Kalman filter algorithms  State estimator algorithms  Vector control algorithms  Pulse width modulation (PWM) Benefits Benefits  Cancel mechanical resonance  Reduce sensor noise  Estimate multiple variables  Real-time axis transformation  Improve motor control

11. Introduction Function Function  High order PID control loop  High sample rate  Time division multiplexing  Fuzzy set control algorithms Benefits Benefits  Precise control  High system bandwidth  Several control system implementations with 1 DSP device  “Intelligent” control

12. Introduction Function Function  Dead band controller  State controller  Power factor correction  FFT algorithms  Adaptive control algorithms Benefits Benefits  Quick settling time  Control many variables  Reduce motor power loss  Analyze mechanical resonance  Reduce disturbance effects

13. DSP CORE

14. Core Architecture MultiplierMultiplier DataMemoryDataMemory ProgramMemoryProgramMemory ALU/ShiftersALU/Shifters Peripherals Controller A(15-0) D(15-0) Program Bus Data Bus MemoryMappedRegistersMemoryMappedRegisters SystemInterface Module * * ‘C240 Only Peripherals (Event Mgr)

15. Core Architecture MUX T (16) MULTIPLIER P (32) SHIFTER (-6, 0, 1, 4) SHIFTER (0-16) MUX ACCH (16) SFL (0-7) C Data Bus 16 32 ALU (32) 32 32 32 16 16 16 32 32 ACCL (16) 1616 16 16 32

16. Core Architecture Data Bus STACK (8x16) PC PC Program ROM / FLASH Address Instruction To Data Memory MUX MUX MUX D(15-0) A(15-0) 12-15 16 16 16 16 16 16 16 16 16 16 16 16 Program Bus

17. Peripheral

18. Clock Signals crystal x4PLL Clock Module x4PLL 39.0625 kHz Prescaler Watchdog WDCLK CPUCLK XTAL1 XTAL2 Event Manager Core Memory External Memory Interface SPISCICANCPU Prescaler ADC ADCCLK CLKOUT

19. Architecture Data Bus Program Bus AR0(16) AR1(16) AR2(16) AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) ARAU(16) ARP(3) ARB(3) DP(9) DataRAM MUX MUX MUX MUX From Program Memory Data / Program RAM 16 16 16 16 16 16 16 16 16 16 16 16 9 7 LSB From IR 16 3 9 16 3 3 3

20. Architecture Event Manager GP Timers Compare Unit PWM Outputs Dead-Band Logic Capture Unit QuadratureEncoder Pulse (QEP) Data Bus Watchdog Timer SCI SPI A/D Converter I /O Pins CAN Non-EV Manager SystemInterfaceModule (‘F/C240 only)

21. Watchdog Timer 6 - Bit Free - RunningCounter CLR /2 /4 /8 /16 /32 /64 WDCLK SystemReset 101 100 011 010 001 000 111 110 8 - Bit Watchdog Counter CLR One-CycleDelay Watchdog Reset Key Register 55 + AA Detector Good Key Bad Key 1 0 1 / / 3 3 WDCR. 2 - 0 WDCR. 6 WDPS WDDIS WDCNTR. 7 - 0 WDCR. 5 - 3 WDCHK 2-0 Bad WDCR Key

22. Power Manager Low Power Mode Normal Run Idle 1 Idle 2 HaltComments CPU off All Peripherals off (except watchdog) Oscillator & Watchdog off Power ~80 mA @ 20 MIPS ~ 50 mA ~ 7 mA ~ < 1 mA Note: PLL is on all the time for ‘X241/2/3!

23. Interrupt NMI ‘ C24x CORE 2 non-maskable interrupts (RS, NMI) 6 maskable interrupts (INT1 - INT6) INT1 INT5 INT2 INT3 INT4 INT6 RS

24. System Reset Watchdog Timer RS pin active To RS pin RS ‘C24x Core

25. Reset ‘C24x RS 10K V cc ExternalDevice reset RS 17 CPUCLK cycles 8 cycles min. Reset Vector Fetched RS pin must be held low a minimum of one CPUCLK RS pin must be held low a minimum of one CPUCLK cycle to ensure recognition of a reset cycle to ensure recognition of a reset Once a reset source is activated, RS pin is driven low Once a reset source is activated, RS pin is driven low for 8 CPUCLK cycles minimum for 8 CPUCLK cycles minimum

26. Event Management EV and Non-EV PeripheralsXINT1 XINT2 PDPINT NMI RS EV and Non-EVPeripheralInterface Internal Sources External Sources NMI ‘C24x CORE INT1 INT5 INT2 INT3 INT4 INT6RS

27. Event Management INT1 INT2 INT3 1 0 1 ‘C24x Core (INTM) “Global Switch” (IMR) “Switch” (IFR) “Latch”CoreInterrupt

28. Event Management Arbitrator FlagEnable XINT1 Flag XINT2 Flag ADCINT To Core InterruptINT1 Enable Enable Polarity Polarity

29. Event Management INT1INT2INT3INT4INT5INT6 Capture 1,2,3 Timer 2 Compare 1,2,3 Timer 1 Compare 1,2,3 Timer 1 EV ADC (low priority) XINT1,2 (low priority) ADC (low priority) XINT1,2 (low priority) SPI, SCI, CAN (low priority) XINT1,2 (high priority) SPI, SCI, CAN (high priority) ADC (high priority) XINT1,2 (high priority) SPI, SCI, CAN (high priority) ADC (high priority) NonEV Core PDPINTPDPINT

30. Latency   delay between an interrupt request and the first interrupt specific code fetch TMS320C24x Latency Components   Peripheral interface time (synchronization)   CPU response time (core latency)   ISR branching time (ISR latency)

31. Stack Operation ACCL PC PUSHPOP 8-LEVEL HARDWARESTACKPOPD PSHD DATA MEMORY INT CALL RET  Hardware stack is expandable to data memory using PSHD/POPD

32. Protection  Interrupt latency may not protect hardware when responding to over current through ISR software  PDPINT has a fast, clock independent logic path to high- impedance the PWM output pins (~ 45-55 ns) DSPCOREDSPCORE PWMOUTPUTS PDPINT Enable OverCurrentSensorOverCurrentSensor ‘C24x PDPINTflagPDPINTflag clock synch.

33. Timer GP Timer Stop/HoldStop/Hold Up Counting Up/Down Counting ContinuousContinuous ContinuousContinuous DirectionalDirectional

34. Timer Architecture TxCNTTimerCounterTxCNTTimerCounter TxPR Period Register TxPR Buffer Buffer CompareLogicCompareLogic 16 PrescaleCountersPrescaleCounters clockingsignal TMRDIRpin auto-load on underflow MUX TMRCLKpin CPUCLK (internal DSP)

35. UP Timer 0 1 2 3 0 1 2 3 0 1 2 CPUCLK TxCNT Reg. TxCON[6] CPU writes a 2 to period reg. buffer anytime here TxPR=2 is auto-loaded on underflow here This example: TxPR = 3 (initially) Prescale = 1 0 1 2

36. U/D Timer CPUCLK TxCON[6] 0 1 2 3 TxCNT Reg. 2 1 0 1 2 1 2 1 0 1 0 CPU writes a 2 to period reg. buffer anytime here TxPR=2 is auto-loaded on underflow here This example: TxPR = 3 (initially) Prescale = 1 Seamless up/down repetition Up/down count period is 2*TxPR

37. PWM Architecture PWM Circuits Output Logic GP Timer 1 Compare GP Timer 1 GP Timer 2 Compare GP Timer 2 Full Compare 1 Full Compare 2 Full Compare 3 Capture Units MUXQEPCircuitWaveformGenerator Output Logic WaveformGenerator EV Control Registers / Logic Reset INT2, 3, 4 TMRCLK / TMRDIR / 2 ADC Start Data Bus CLK DIR T1PWM/T1CMP T2PWM/T2CMP PWM1/CMP1 PWM2/CMP2 PWM3/CMP3 PWM4/CMP4 PWM5/CMP5 PWM6/CMP6 CAP1/QEP1 CAP2/QEP2 CAP3

38. TIMER CPUCLK TxCNT Reg. TxCON[6] 0 1 230 1 230000033TMRDIR Count holds at TxPR=3 since TMRDIR = hi on rising clock edge 2 CPUCLK latency This example: TxPR = 3 Prescale = 1 CPUCLK as source

39. PWM Architecture This example: TxCON.3-2 = 00 (reload TxCMP on underflow) TxPR = 3 TxCMP = 1 (initially) Prescale = 1 0 1 2 3 0 1 2 3 0 1 2 CPUCLK TxCNT Reg. 3 0 CPU writes a 2 to compare reg. buffer anytime here TxCMP=2 is loaded here TxPWM/TxCMP (active high) TxCINT

40. PWM Architecture CPUCLK 0 1 2 3 TxCNT Reg. 2 1 0 1 2 0 3 2 1 TxPWM/TxCMP (active high) This example: TxCON.3-2 = 01 (reload TxCMP when on underflow or period match) TxPR = 3 TxCMP = 1 (initially) Prescale = 1 TxCMP loads with a 1 TxCMP loads with a 2 TxCMP loads with a 1

41. PWM Architecture CMPRx compare register CMPRx Compare Reg. Buffer Compare CompareLogicCompareLogic 16 sym.asym.sym.asym. OutputLogic PWMy/ CMPy CMPy T1CNT (GP Timer 1) auto-load on software selectable events SVSV DeadBandDeadBand MUXMUX

42. Space Vector

43. VaVbVc DTPH1DTPH2DTPH3DTPH1DTPH2 DTPH31 2 3 5 46 3-Phase Power Converter GNDVs Only states of transistors 1, 3, & 5 need be determined since 2, 4, & 6 are their respective compliments Switching State Notation: (Q5,Q3,Q1) e.g. (0,0,1) means gate 1 is on, gates 3 & 5 are off e.g. (0,0,1) means gate 1 is on, gates 3 & 5 are off

44. Space Vector Y-Connected Motor Windings Showing Current Flow (Q5,Q3,Q1) = (001)  V a =V s, V b =V c = GND Vc 60° V a V b 60° i i/2 i/2 Voltage Drop Vectors yx 2V s /3 V s /3

45. Space Vector Basic Space Vectors w/ Switching Patterns U 180 (110) U 300 (101) U 0 (001) U 240 (100) U 120 (010) U 60 (011) O(000) O(111)

46. Space Vector Approximate desired voltage drop vector as a linear combination of the basic space vectors Coefficients are duration times U 0 (001) U 60 (011) Uout T 1 T 2

47. Space Vector DTPH1 DTPH2 DTPH3 O(111) U 0 (001) U 60 (011) U 0 (001) U 60 (011) Full compare #1 match Full compare #2 match O(111) GP Timer 1 value T 1 /2 T 2 /2 T p /2 T1PR match

48. PWM to motor phase supply rail Gate Signals are Complimentary PWM  Transistor gates turn on faster than they shut off  Short circuit if both gates are on at same time!

49. Asymmetric PWM Example PHx DT dead time prescalerprescaler Counter8-bit ENA reset CPUCLK (20 MHz) ComparatorComparator 4-bit period (DBTCON.11-8) (DBTCON.11-8) DTPH x DTPH x_ PH x DT edgedetectedgedetect Clock DTPH x DTPH x_

50. A/D Converter Ch. 0-7 Sample & Hold Sample 10 bit A/D Converter Converter 2-Level FIFO Internal Data Bus VREFHI VREFLO ADCSOC Control&ReferenceCircuitry 8/1MUX VCCA AGND 5 volts GND Event Manager SOC Signal

51. Q&A

52. Thanks