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Routing Tree Construction with Buffer Insertion under Obstacle Constraints Ying Rao, Tianxiang Yang Fall 2002
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Buffer Insertion for Elmore delay Purpose: reduce Elmore delay. Purpose: reduce Elmore delay. Elmore delay model: Elmore delay model:
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Buffer Insertion for Elmore Delay (Cont.) Key to buffer insertion in optimizing delay: Key to buffer insertion in optimizing delay: Isolation property
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Problem Formulation Given: A source and multiple sinks on a routing grid with wiring obstacles and buffer blockage. Given: A source and multiple sinks on a routing grid with wiring obstacles and buffer blockage. Find: A routing tree from source to all sinks with feasible buffers insertions in the presence of obstacles, such that the maximum delay from source to sinks is minimized. Find: A routing tree from source to all sinks with feasible buffers insertions in the presence of obstacles, such that the maximum delay from source to sinks is minimized.
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Definitions “Wire path”: A path connecting two nodes by wires only with no buffers between. “Wire path”: A path connecting two nodes by wires only with no buffers between. “Buffered Path”: A path connecting two nodes with buffer inserted “Buffered Path”: A path connecting two nodes with buffer inserted
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Definitions (Cont.) “Buffer Combination”: A tree component connecting three or more nodes without internal buffers. “Buffer Combination”: A tree component connecting three or more nodes without internal buffers. “BC-Subtree”: A subtree beginning with a buffer combination. BC-Subtree is a special subtree. “BC-Subtree”: A subtree beginning with a buffer combination. BC-Subtree is a special subtree.
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Lookup Tables “Wire path table ”: a table storing pre-computed optimal buffer to buffer (wiresizing) solutions for wire paths. “Wire path table ”: a table storing pre-computed optimal buffer to buffer (wiresizing) solutions for wire paths. “Buffered combination table”: A table storing pre-computed optimal (wiresizing) solutions for buffer combinations. “Buffered combination table”: A table storing pre-computed optimal (wiresizing) solutions for buffer combinations. “Buffered path table”: A table storing pre-computed optimal solutions for buffered path. “Buffered path table”: A table storing pre-computed optimal solutions for buffered path.
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Wire path table “Wire path table ”: a table storing pre-computed optimal buffer to buffer (wiresizing) solutions for wire paths. “Wire path table ”: a table storing pre-computed optimal buffer to buffer (wiresizing) solutions for wire paths. The minimum delay of a wire path from one node u to another node v is a function of d(u,v) – shortest distance between u and v, the driver resistance in u and the load capacitance in v. Thus the table can be pre-calculated and stored in the wire path (lookup) table. The lookup entry is (b u,b v,d(u,v)).
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Buffer Combination Table “Buffered combination table”: A table storing pre-computed optimal (wiresizing) solutions for buffer combinations. “Buffered combination table”: A table storing pre-computed optimal (wiresizing) solutions for buffer combinations. The delay of a buffer combination (v, r 1, r 2, …, r t ) is a function of distance configuration of the buffer combination, the driver resistance of v and the load capacitances of r i (i=1,2,…,t) Degree of buffer combination (=t+1) is small in practice (or it will cause large delay). We can restrict the maximum degree of a buffer combination so that the distance configuration can be obtained by computing a steiner tree of a small number of nodes.
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Buffered Path Table “Buffered path table”: A table storing pre-computed optimal (wiresizing) solutions for buffered path. “Buffered path table”: A table storing pre-computed optimal (wiresizing) solutions for buffered path. Distance from u to v is computed by considering all possible buffer insertion combinations (using BP-Graph). With lookup entry being ((u,v), path between u and v), the solution to lookup is the buffer locations along the path and minimum delay between u and v. Distance from u to v is computed by considering all possible buffer insertion combinations (using BP-Graph). With lookup entry being ((u,v), path between u and v), the solution to lookup is the buffer locations along the path and minimum delay between u and v.
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Optimal BC-subtree “BC-subtree”: A subtree beginning with a buffer combination. “BC-subtree”: A subtree beginning with a buffer combination. Enumerate all possible buffer combinations rooted at v (driver), we get all possible BC-subtrees. Delay of any BC-subtree can be calculated immediately using buffered path table and buffer combination table.
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Optimal Subtree For a more general form of subtree with two sinks (as in the following example). Combine t 1 and t 2 to node T. Construct graph G T with node T and other buffer nodes. For a more general form of subtree with two sinks (as in the following example). Combine t 1 and t 2 to node T. Construct graph G T with node T and other buffer nodes. The shortest path from T to each other vertex v corresponds to the optimal subtree connecting to t 1 and t 2. Apply sinlge-source shortest path algorithm (such as Dijkstra’s algorithm), we get all optimal subtrees for every node.
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Optimal Subtree (Cont.) Algorithm proceeds to create subtrees by increasingly considering more sinks. Algorithm proceeds to create subtrees by increasingly considering more sinks.
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Algorithm Formulation
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Algorithm Complexity Time Complexity Time Complexity O((t+1) k |B| t+1 |N| t+1 ) Space Complexity Space Complexity O(2 k |B||N|)
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References X. Tang, R Tian, H Xiang, D.F. Wong “A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints”, ICCAD, pages 49--56, 2001 X. Tang, R Tian, H Xiang, D.F. Wong “A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints”, ICCAD, pages 49--56, 2001 M. Lai, D.F. Wong, “Maze Routing with Buffer Insertion and Wiresizing”, IEEE Transaction on CAD of Integrated Circuits and Systems, 2002 M. Lai, D.F. Wong, “Maze Routing with Buffer Insertion and Wiresizing”, IEEE Transaction on CAD of Integrated Circuits and Systems, 2002 The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1997 The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1997 W. C. Elmore, “The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers”, J. Applied Physics, 1949 W. C. Elmore, “The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers”, J. Applied Physics, 1949 L. He, “VLSI Interconnects”, UW ECE902 Notes, Fall 1999 L. He, “VLSI Interconnects”, UW ECE902 Notes, Fall 1999 J. Lillis, C. K. Cheng, and T. T. Y. Lin, “Optimal Wiresizing and Buffer Insertion for Low Power and A Generalized Delay Model”, Proceedings of IEEE International Conference on Computer-Aided Design, 1995 J. Lillis, C. K. Cheng, and T. T. Y. Lin, “Optimal Wiresizing and Buffer Insertion for Low Power and A Generalized Delay Model”, Proceedings of IEEE International Conference on Computer-Aided Design, 1995
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