1. Sonar Sensor Project Polaroid Sonar Sensor Details of the Project
Measuring Distance with Sound Waves
Overview of the Sensor Module
Details of the Project
Sonar Circuit and Processor
Concept of Handshaking
Sensor and Processor FSMs
Calculation of Velocity
ECE M. A. Jupina, VU, 2013

2. Particulars of the Sonar Sensor
Range is six inches to 35 feet
16 cycles at 49Khz
Listen for return pattern
Sound travels ~0.9 ms/ft
Timer on DE2 determines distance
Transducer
Transmitter/Receiver
OBJECTIVE: Use a Polaroid 6500 Sonar Ranging Module interfaced to an Altera DE2 board to measure position and speed of a person standing 2 to 7 feet away from the sensor. The position and velocity of a person will be displayed on the seven segment displays on the DE2 board.
Position resolution: 1 foot and Velocity resolution: foot/sec
Transducer – a device that converts input energy of one form into output energy of another. Here, the piezoelectric transducer either converts electrical energy into mechanical energy when it generates a sound wave or converts mechanical energy from a sound wave into electrical energy when receiving a signal.
ECE M. A. Jupina, VU, 2013

3. Ultrasonic Transducer and Circuitry
The sensing is initiated by first creating a sonic ping at a specific frequency.  In the case of the Polaroid module, the ping is roughly 16 high-to-low transitions between +200v and -200v.  These transitions are fed to the transducer at around 50 kHz.  For reference, the human ear can hear sounds in roughly the 20 Hz to 20 kHz range.  As this chirp falls well out of the range of human hearing, the ping is not audible.  You can hear the transducer click as the chirp is sent.
Sound waves above the audio range (20 Hz – 20 KHz) are transmitted and received by the sensor so as to ascertain the
location of an object.
ECE M. A. Jupina, VU, 2013

4. Speed of Sound Sound waves travel at 330 meters-per-second or
1082 feet-per-second
1.082 feet-per-millisecond
~0.9 millisecond-per-foot.
The chirp moves radially away from the transducer through the air at approximately 330 m/s, the speed of sound.  This is roughly 0.9ms/foot.  This speed is only slightly affected by humidity and virtually not affected at all by pressure and therefore is almost independent of altitude. 
ECE M. A. Jupina, VU, 2013

5. Using Sound Waves to Measure Distance
Object
Sensor X
Since the chirp is spreading out radially, the signal strength as the chirp moves farther from the transducer is reduced by 1/d2.  This means that the maximum measuring distance drops off rapidly at the extreme maximum of the sensor.
When the chirp reaches an object, it is reflected in varying degrees dependent on the shape, orientation, and surface properties of the reflecting surface.  The Polaroid ranging system is capable of detecting small obstacles such as a flower stem at several meters.
This reflected chirp then travels back towards the transducer, again at the speed of sound.  The transducer is especially sensitive to noises around 50 kHz like the chirp.  As the reflected signal hits the transducer, a voltage is created which is fed to a stepped-gain amplifier of the 6500 module.
Since the signal decreases in strength with distance at an inverse squared proportion, the gain of the amplifier is increased exponentially (~d2).  This helps to give the best sensitivity across the range of the detector which is roughly 2 feet to 35 feet.
Once the 6500 ranging module "sees" enough cycles of the reflected signal, it changes it's ECHO output to reflect the received reflected signal or echo.  All that is left to do is to measure the time from the initiation of the ping to the received echo.  This time corresponds directly to the distance traveled by the ping.
The transmitted and reflected sound waves travel a total distance 2X.
Therefore,
total travel time = (0.9ms/ft)(2X)
ECE M. A. Jupina, VU, 2013

6. Polaroid 6500 Sonar Ranging Module
The 6500 Series is an economical sonar ranging module with a simple interface that is able to measure distances from 6 inches to 35 feet. The typical accuracy is +/- 1% of the reading over the entire range.
This module has an external blanking input that allows selective echo exclusion for operation on a multiple-echo mode. The module is able to differentiate echoes from objects that are only three inches apart. The digitally controlled gain, variable bandwidth amplifier minimizes noise and side-lobe detection in sonar applications.
The module has an accurate ceramic resonator controlled 420 kHz time base generator. An output based on the 420 kHz time base is provided for external use. The sonar transmit output is 16 cycles at a frequency of 49.4 kHz.
The 6500 Series module operates over a DC power supply range from 4.5 volts to 6.8 volts (5 volts nominal) and is characterized for operation from 0° C to 40° C.
ECE M. A. Jupina, VU, 2013

7. Circuit Diagram Transducer Digital IC:
The TL851 is an economical digital I2L ranging control integrated circuit designed for use with the SN28784 sonar ranging receiver IC. The TL851 is designed for distance measurement from 6 inches to 35 feet. The device has an internal oscillator that uses a low-cost external ceramic resonator. With a simple interface and a 420 kHz ceramic resonator, the device will drive a 50 kHz electrostatic transducer. The device cycle begins when initiate (INIT) is taken to the high logic level. There must be at least 5 ms from initial power up (Vcc) to the first initiate signal in order for all the device internal latches to reset and for the ceramic resonator controlled oscillator to stabilize. The device will transmit a burst of 16 pulses each time INIT is taken high. The oscillator output (OSC) is enabled by INIT. The oscillator frequency is the ceramic resonator frequency divided by 8.5 for the first 16 cycles (during transmit) and then the oscillator frequency changes to the ceramic resonator frequency divided by 4.5 for the remainder of the device cycle. When used with an external 420 kHz ceramic resonator, the device internal blanking disables the receive input (REC) for 2.38 ms after initiate to exclude false receive inputs that may be caused by transducer ringing. The internal blanking feature also eliminates echoes from objects closer than 1.3 ft. from the transducer. If it is necessary to detect objects closer than 1.3 feet then the internal blanking may be shortened by taking the blanking inhibit (BINH) high, enabling the receive input. The blanking input (BLNK) may be used to disable the receive input and reset ECHO to a low logic level at any time during the device cycle for selective echo exclusion or for a multiple-echo mode of operation. The device provides a synchronous 4-bit gain control output (12 steps) designed to control the gain of the SN28784 sonar ranging receiver IC. The TL851 operates over a supply voltage range of 4.5 volts to 6.8 volts (+5 volts DC nominal voltage) and is characterized for operation from 0°C to 40°
ECE M. A. Jupina, VU, 2013

8. Circuit Diagram Transducer Analog IC:
The SN28784 is an economical sonar ranging receiver IC for use with the TL851 digital control IC. A minimum of external components is required for operation, and this amplifier easily interfaces to 50-kHz electrostatic transducers. An external resistor from BIAS (pin 8) to GND (pin 16) provides the internal biasing reference. The amplifier’s gain can be set with a resistor from G1IN (pin 1) to GADJ (pin 3). Digital control of amplifier gain is provided with gain control inputs GCA, GCB, GCC, and GCD. These inputs must be driven synchronously (all inputs stable within 0.1 ms) to avoid false receive output signals due to invalid logic counts. This can be done easily with the TL851 control IC. To dampen ringing of the 50-kHz electrostatic transducer, a 5000 ohm resistor from G1IN to XIN is recommended. An external parallel combination of inductance and capacitance between LC and VCC provides an amplifier with an externally controlled gain and Q. This not only allows control of gain to compensate for attenuation of signal with distance, but also maximizes noise and sidelobe rejection. Care must be taken to accurately tune the LC combination at operating frequency or gain and Q will be greatly reduced at higher gain steps. AC coupling between stages of the amplifier is accomplished with a 0.01 microfarad capacitor for proper biasing. The receive output is normally held at a low level by an internal 1 mA current source. When an input of sufficient amplitude is received, the output is driven alternately by the 1 mA discharge current and a 50 mA charging current. A 1000 pF capacitor is required from REC to GND to integrate the received signal so that one or two noise pulses will not be recognized. XIN provides clamping for the transformer secondary when used for transducer transmit drive. The SN28784 operates over a supply voltage of 4.5 volts to 6.8 volts (+5 volts DC nominal voltage) and is characterized for operation from 0°C to +40°C.
ECE M. A. Jupina, VU, 2013

9. Schematic Equivalent Circuits of Polaroid Module’s Inputs and Outputs
The echo output is an open collector transistor output
and requires a 4.7 KW pull-up resistor between VCC
and the output.
ECE M. A. Jupina, VU, 2013

10. Ultrasonic Source/Detector
Features:
50 kHz Electrostatic Transducer
Beam Angle of 15° at -6 dB
For Ranges from 6” to 35’
Resolution: ± 1% over entire range
Excellent Receive Sensitivity (-42 dB min at 50.0 kHz for 150 VDC bias)
0dB = 1 volt/µPa where Pa are units of pressure
The transducer generates 1 volt for each µPa of air pressure sensed.
1 Pa = 1.45x10-4 lb/in2
Perforated Protective Cover
Specifically Intended for Operation in Air at Ultrasonic Frequencies
This transducer is ideally suited for applications where the most sensitivity possible is the highest priority. This ultrasonic transducer is among the best available when detecting soft targets. It has a broad band frequency response.
ECE M. A. Jupina, VU, 2013

11. Detector Sensitivity versus Frequency
Polaroid detector has a maximum sensitivity at ~50 KHz.
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12. Ultrasonic Detection – Highly Directional
Main Beam
Object a
Transducer
Side
Lobes
Transducer
In order to properly select a transducer for a given application, it is important to be aware of the principles of sound propagation. Since sound is a wave phenomenon, its propagation and directivity are related to its wavelength (lambda). A typical radiation power pattern for either a generator or receiver of waves is shown above. Due to the reciprocity of transmission and reception, the graph portrays both power radiated along a given direction (in the case of wave production), and the sensitivity along a given direction (in case of wave reception).
The angular, half-width (alpha/2) of the main beam is given by:
Sin (alpha/2) =lambda/D = V/DF
Where “D” is the effective diameter of the flexure diaphragm, “V” is the velocity of sound (330 meter/second in air), and “F” is the operating frequency. The above relationship applies if lambda < D. For lambda > D, the power pattern tends to become spherical in form. Thus, narrow beams and high directivity are achieved by selecting “D” large in relation to lambda.
As an example of a typical situation, a transducer with an effective diameter of 1.5 inches ( m) will produce a main beam with full width alpha of 20° at a frequency of 50 KHz (lambda = m = 0.26 inches).
At 0o : detected signal = -3dB = 0.5 source signal
At 30o : detected signal = -20dB = 0.01 source signal
ECE M. A. Jupina, VU, 2013

13. Sonar Sensor Signals Data Request Signal Data Ready Signal
Power is turned-on
Data Request Signal
~0.02ms
1/2E-5 = 50 KHz
External Trigger
16 cycles at 49.4 KHz
sent by the transducer
Control lines tied low
Detector turned-off
There are two basic modes of operation for the 6500 Series Sonar Ranging Modules: Single-echo mode and multiple-echo mode. The application of power (VCC), the application of the initiate (INIT) input, and the resulting transmit output, and the use of the Blanking Inhibit (BINH) input are basically the same for either mode of operation. After applying power (VCC) a minimum of 5 milliseconds must elapse before the INIT signal can be taken high. During this time, all internal circuitry is reset and the internal oscillator stabilizes. When INIT is raised to a high level, drive to the transducer (XDCR) output occurs. Sixteen pulses at 49.4 kHz with an amplitude of 0 volts to 400 volts peak to peak will excite the transducer as transmission occurs. At the end of the 16 transmitted pulses, a 200 VDC bias remains on the transducer for optimum receiving operation.
In order to eliminate ringing of the transducer from being detected as a return signal, the Receive (REC) input of the ranging control IC is inhibited by internal blanking for 2.38 milliseconds after the initiate signal. If a reduced blanking time is desired, then the BINH input can be taken high to end the blanking of the Receive input any time prior to internal blanking. This may be desirable to detect objects closer than 1.33 feet (corresponding to 2.38 milliseconds) and may be done if transducer damping is sufficient so that ringing is not detected as a return signal.
Data Ready Signal
Transducer receives
reflected signal
Total Travel Time
Measurement range is six inches (due to internal blanking) to 35 feet (due to sensitivity)
ECE M. A. Jupina, VU, 2013

14. System Diagram SONAR SYSTEM PROCESSOR Data Request FSMs Data Ready
4-bits
Sonar
Circuit
Data Bus
Registers
ALU
DATA
Sonar system contains the transducer, the transducer support circuitry, and the “Sonar Circuit” that resides on the DE2 board. The sonar circuit contains a counter circuit that captures the time it takes for an ultrasonic signal to travel from and back to the transducer. This 8-bit count value will also be converted into a 4-bit position value by a shift circuit that resides within the Sonar Circuit.
The Processor will be responsible for the control (FSMs), data storage (current and previous position and current velocity), and the calculation of the velocity of an object in front on the sensor.
To transmit data between the systems, it is often necessary to provide what are called “handshaking” signals (Data Request and Data Ready) that ensure that the data is received correctly, particularly when the two systems are running at very different speeds. Consider the situation above, in which 4-bits of data are to be transmitted from the Sonar System to the Processor.
ECE M. A. Jupina, VU, 2013

15. “Handshaking” Signals
When the Processor requires new data, it raises the Data Request line high (to “1” ).
Once the Sonar System sees this and has placed the correct data on the 4-bit Data lines, it raises the Data Ready line high.
When the Processor has taken the data (typically stored in a D-register) it lowers the Data Request line.
After this, the Sonar System lowers the Data Ready line.
The Processor can only issue a new request after the Data Ready line is lowered.
When the Processor requires new data, it raises the Data Request line high (to “1” ). Once the Sonar System sees this and has placed the correct data on the 4-bit Data lines, it raises the Data Ready line high. When the Processor has taken the data (typically stored in a D-register) it lowers the Data Request line after which the Sonar System lowers the Data Ready line. The Processor can only raise a new request after the Data Ready line is lowered. This procedure is called a “full handshake” and ensures that the data is transferred correctly, even when the two systems are running at vastly different speeds. We will make use of this concept in this practicum project, because the Processor will be running at the System Clock frequency, and the Sonar System will be running at a much slower speed (1 Hz).
ECE M. A. Jupina, VU, 2013

16. Sonar Project Circuit
Clock_50MHz ?
CLK_DIV block divides-down the 50 MHz crystal oscillator on the DE2 board to various clock frequencies. You will need to select the correct system clock frequency so that the counter block in the Sonar Circuit correctly captures the total travel time of the sonar signal.
The LPM_ABS Block generates the magnitude or absolute value of the velocity.
DEC_7SEG Blocks drive 7-segment LED displays on the DE2 board that can display 4-bit hexadecimal values (position and velocity values will be shown here).
ECE M. A. Jupina, VU, 2013

17. The Sonar Counter Circuit
The sonar module can be trigger (or initialized) up to 10 times every second (We will only trigger it once a second so a 1 Hz square wave will be used).
A counter is used to measure the total travel time of the sound wave. The counter measures the time (actually the number of clock cycles) between the rising edge of the INIT or Data Request signal and the rising edge of the ECHO or Data Ready signal.
The rising edge of Data Request signal triggers the counter to begin counting and the rising edge of the Data Ready signal triggers the registers in the counter block to store the count.
ECE M. A. Jupina, VU, 2013

18. Sonar Circuit Block 8-bit Counter Divide by 16 8-bits 4-bits CLOCK
Remember that the sonar signal travels a total distance of 6 feet for an object 3 feet from the transducer.
54 / 16 is approximately 3 (round down to the nearest integer value – resolution is to be within one foot).
NOTE:
A divide by 18 block would be required for an exact calculation. However, this requires a much more complicated divider circuit than a 2N divider circuit. Thus, a divide by 16 circuit will suffice over the measurement range of 2 to 7 feet.
CLOCK
Cycles
Position
in feet
What is the system clock frequency if 54 clock cycles
are to represent a measured distance of 3 feet?
ECE M. A. Jupina, VU, 2013

19. Position Measurement
The Sonar Count is divided down to a number to represent the position in feet. The position is updated once every second.
The position of a person standing 2 to 7 feet away from the sonar sensor will be sensed.
Going beyond 8 feet will cause erroneous values since the error is greater than 1 foot due to the divide by 16 circuit being used instead of the divide by 18 implementation.
Examples:
Divide by 18 (exact)
A count of 126 = 7 feet
A count of 144 = 8 feet
Divide by 16 (approximate)
126/16 = 7.875, a value of 7 feet is shown on display, error=0.875 feet
144/16 = 9, a value of 9 feet is shown on the display, error = 1 foot !
ECE M. A. Jupina, VU, 2013

20. SONARCIRCUIT.BDF
The sonar circuit contains a counter circuit that captures the time (the number of clock cycles) it takes for an ultrasonic signal to travel from and back to the sensor. This 8-bit count value will then be converted into a 4-bit position value in feet by a shift circuit that resides within the Sonar Circuit. Only the four least significant bits are required for the DataOut signal.
The DataReq (data request) signal from the PROCESSOR Block (SENSORFSM within this block actually generates it) triggers the counter to begin the count on every System Clock cycle. The DataReq signal is also used to trigger or initialize the Polaroid 6500 module to send out the ultrasonic signal.
When the ECHO signal from the 6500 module goes HIGH, the counter stops counting. The Data Rdy signal is generated by the ECHO signal coming from the Polaroid 6500 module. The DataRdy line also goes HIGH to tell the Processor Block that the data is ready for processing.
WIRE elements in the primitives, buffer library are used to isolate the input and output signals from each other.
For the “divide-down” or shift circuit needed for the Sonar Circuit, go to the gates library under megafunctions and select the module LPM_CLSHIFT.
ECE M. A. Jupina, VU, 2013

21. SONARCOUNT.VHD
When the Data Request (INIT signal for counter and transducer) is LOW the counter is set to zero. When it goes HIGH the count begins and continues on each clock cycle until the ECHO or Data Ready line goes HIGH. When the ECHO line goes HIGH, the final count is stored.
ECE M. A. Jupina, VU, 2013

22. Sonar Count Simulation
When the Data Request (INIT signal for counter and transducer) is LOW the counter is set to zero. When it goes HIGH the count begins and continues on each clock cycle until the ECHO or Data Ready line goes HIGH. When the ECHO line goes HIGH, the final count is stored.
ECE M. A. Jupina, VU, 2013

23. LPM_CLSHIFT
The Altera Quartus II software provides you with a number of pre-designed units, which they call Library of Parameterized Modules (LPM). These consist of adders, adder/subtraction, multipliers, shift registers, decoders and more – basically everything you need to design a digital system. The meaning of the word “parameterized” here is that you can specify many different things about the module. For example, you can call up an adder and specify that it should be a 10 bit adder, or a 20-bit adder. You can specify that a multi-bit D register has an enable signal (or not).
To look at the different modules that are available, go to Edit, Insert Symbol and look under the libraries, megafunctions subdirectory.
For the “divide-down” or shift circuit needed for the Sonar Circuit, go to the gates library under megafunctions and select the module LPM_CLSHIFT.
ECE M. A. Jupina, VU, 2013

24. LPM_CLSHIFT Parameters
Screen captures above show how to configure the LPM_CLSHIFT module.
You will need to set up a logical, 8-bit shift circuit with a direction input (left or right) and a distance input (the number of bits to shift in binary).
To learn more about the various parameters of this module, click on the “Documentation” button in the dialog box.
ECE M. A. Jupina, VU, 2013

25. SONARCIRCUIT.BDF VCC Or GND
To control the LPM_CLSHIFT module, the 3-bit input “distance” controls the number of bits to shift (for example, the shift distance can be 0 to 7 for a 8-bit number).
The direction input controls whether the shift is to the left or right.
The VCC and GND primitive library elements are used to set the distance and direction of the shift function.
ECE M. A. Jupina, VU, 2013

26. Sonar Circuit Simulation
Sonar Count and LPM_CLSHIFT together.
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27. PROCESSOR Block
A 1 Hz clock signal and the DataRdy signal from the Sonar Circuit block (generated by the ECHO signal from 6500 module) are used to determine the STATE of the SENSOR FSM. Depending on the STATE of the SENSOR FSM, the DataReq signal is normally LOW but goes HIGH when the 1 Hz clock signal goes HIGH but the DataRdy signal remains LOW.
The DataIn signal is the 4-bit Position value from the output of the SONAR CIRCUIT Block.
REG A stores the current Position value in feet and REG B stores the current magnitude of the Velocity in ft/s. These values are updated once every second.
ECE M. A. Jupina, VU, 2013

28. PROCESSOR.BDF Register A: Current Position
The position is updated once every second. Therefore, by taking the difference between two position values having been measured 1 second apart, we get a value for the velocity in ft/s.
Two FSMs needed here:
Sensor FSM – creates handshaking between 6500 module and processor
Processor FSM – dictates the sequence of events to occur while processing the position data
Register A: Current Position
Register B: Current Velocity
Register C: Previous Position
RegA – RegC: Calculates Velocity
ECE M. A. Jupina, VU, 2013

29. SENSORFSM.VHD
State A – Initial state (1 Hz clock signal is low and ECHO or Data Ready is low)
State B – Data Request goes high
State C – Data is Received and Data Request goes low
State D – Data Ready goes low
Data Request output is generated based on the input “sensor” where sensor = CLK_1Hz & DataRdy (two 1 bit signals)
The 1 Hz clock generates the INIT (of the 6500 module) or DataReq signal of the SENSOR FSM
The ECHO signal (of the 6500 module) generates the DataRdy signal
ECE M. A. Jupina, VU, 2013

30. SENSORFSM.VHD Con’t
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31. SENSOR FSM Simulation
Note: for simulation purposes, the “clk_1Hz” signal is not a 1 Hz square wave.
State A – Initial state (1 Hz clock signal is low and ECHO or Data Ready is low)
State B – Data Request goes high
State C – Data is Received and Data Request goes low
State D – Data Ready goes low
The bottom signal is a buried node signal denoting the STATE y of the SENSORFSM.
ECE M. A. Jupina, VU, 2013

32. PROCFSM.VHD
There are 6 STATES required for the processor to do the following:
1. Register A (or 1) stores the Current Position
2. Calculate the Velocity by taking the difference REGA – REGC
3. Register B (or 2) stores the Current Velocity
4. Register C (or 3) stores the Previous Position
Note: Two PROCESS statements here.
The processor FSM is first triggered on the rising edge of the START signal (START = not(DataReq)).
Then, if Resetn=1, the processor FSM sequences through the STATES A – F on each rising CLOCK edge.
Note:
Once the DataRdy goes HIGH, DataReq goes LOW. Thus, the rising edge of not(DataReq) can be used to trigger the processing of the data.
ECE M. A. Jupina, VU, 2013

33. PROCFSM.VHD Con’t
Finally, the processor FSM is not re-initialized to STATE A until the START signal goes LOW (otherwise it remains in STATE F).
The reason for this is the following:
Once the position data is stored and the velocity is calculated, the processor waits until the new position data is available before performing the storage and subtraction operations again.
ECE M. A. Jupina, VU, 2013

34. PROCFSM.VHD Con’t
You are required to design the FSM to control the processor unit. From your state table fill in the above to complete the procfsm.vhd file.
Input Enables of Registers:
IE1 – Reg A (or 1)
IE2 – Reg B (or 2)
IE3 – Reg C (or 3)
IE4 – Reg X
IE5 – Reg Y
Select Lines of Multiplexer:
SDATA – Data
S1 – Reg A (or 1)
S2 – Reg B (or 2)
S3 – Reg C (or 3)
S4 – Reg Y
AddSub – Add/Subtract function (Add = 0, Subtract=1)
Done – Processor has completed the storage of values and the computation
ECE M. A. Jupina, VU, 2013

35. PROCESSOR FSM Simulation
The speed of the processor is based on the SYSTEM CLOCK signal. Could be run at a higher frequency but not necessary. Running a digital circuit at a lower frequency decreases power consumption.
Initially a count of 54 is stored (54/16=3.375 feet but rounded down to 3 feet).
Then a count of 72 is stored (72/16=4.5 feet but rounded down to 4 feet).
When the Data Request line goes LOW (or when the Inverted Data Request line goes HIGH) the PROCESSOR FSM goes to state B (SENSOR FSM goes to state C) and cycles through all of the states and then remains in state F until the Data Request line goes High and resets the processor to state A.
ECE M. A. Jupina, VU, 2013

36. Sonar Project File for Simulation (SONARPROJECT1.BDF)
The LPM_ABS function is in the megafunctions, arithmetic library. Configure it for 4-bit IO.
When VHDL code is compiled, symbols are automatically generated.
To create symbol blocks of the PROCESSOR.BDF and SONARCIRCUIT.BDF do the following:
If not already opened, open these BDF files and proceed to do the following for each file
Go to File, Create/Update, Create Symbol Files for Current File
Now open the new SonarProject1.bdf file and go to Edit, Insert Symbol, find the processor and sonarcircuit symbol names in the Project library and add these to this BDF file. Finish wiring the above circuit and add IO symbols.
Note: Block symbol names in a BDF file can’t have the same name as the BDF file. A recursive compiler error will result.
ECE M. A. Jupina, VU, 2013

37. Velocity Measurement
The magnitude of a person’s velocity in feet-per-second is determined by a subtraction circuit in the processor block and an absolute value circuit (lpm_abs block). The magnitude of the velocity is updated once every second.
The LPM_ABS function is in the megafunctions, arithmetic library. Configure it for 4-bit IO.
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38. SONARPROJECT1.BDF Close-up view – left side of circuit
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39. SONARPROJECT1.BDF Close-up view – right side of circuit
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40. SONARPROJECT1.VWF
On this time scale, we can observe the SENSOR activity. Processing of the data starts during state C of the SENSOR FSM.
Note: The CLK_1Hz signal is not a 1 Hz signal. For simulation purposes this is not necessary. The frequency of the CLK_1Hz signal only needs to be much less than the system clock frequency.
Zoom in on the shaded region in the next slide.
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41. SONARPROJECT1.VWF Zoom in on the shaded region in the next slide.
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42. SONARPROJECT1.VWF
On this time scale, we can observe the PROCESSOR activity.
ECE M. A. Jupina, VU, 2013

43. Sonar Project File for Testing (SONARPROJECT2.BDF)?
Clock_50MHz
Signals to & from Sensor:
INIT – PIN_D25
ECHO – PIN_J22
System
Clock
Frequency ? ?
Where the question marks are shown, you need to define the proper pin numbers.
CLK_DIV block divides-down the 50 MHz crystal oscillator on the DE2 board to various clock frequencies. You will need to select a system clock frequency so that the counter block in the Sonar Circuit correctly captures the total travel time of the sonar signal (Note: 54 clock cycles represent a measured distance of 3 feet by the sonar sensor).
DEC_7SEG Blocks drive the 7-segment LED displays on the DE2 board that can display 4-bit hexadecimal values (position and velocity values will be shown here).
At the sensor test station, the sonar sensor 6500 module is connected to the Altera DE2 board such that the INIT signal is on pin_D25 (Pin 1 on JP1) and the ECHO signal is on pin_J22 (Pin 2 on JP1). ? ?
ECE M. A. Jupina, VU, 2013

44. Pin Assignments for DE2 Board
Reset is PIN_N25
50 MHz clock is PIN_N2
INIT is PIN_D25 (Pin 1 on JP1)
ECHO is PIN_J22 (Pin 2 on JP1)
Common Ground is Pin 12 on JP1
Seven Segment Displays are …
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45. ECE M. A. Jupina, VU, 2013

46. Clock Inputs
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47. ECE M. A. Jupina, VU, 2013

48. Header Pin Assignments
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49. Header Pin Assignments
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50. ECE M. A. Jupina, VU, 2013

51. Sonar Project Pre-Lab Assignment
Determine the system clock frequency such that 54 clock cycles represent a measured distance of 3 feet by the sonar sensor. Use this frequency to set up the SYSCLK signal in the SONARCIRCUIT.VWF waveform file.
Determine the state diagram and table of the SENSOR FSM.
Determine the state diagram and table and finish the VHDL Code in the procfsm.vhd file so that the following sequence of events can be performed in the Processor Block:
Load the “current” position data into register A.
Calculate the velocity by performing the following subtraction: RA–RC.
Load the velocity data into register B.
Load the “previous” position data into register C.
Deliverables:
Detailed calculation of the system clock frequency
2 state tables
2 state diagrams
1 VHDL file.
Note: Subtraction operation will require more than one clock cycle.
ECE M. A. Jupina, VU, 2013

52. Sonar Sensor Practicum Work
Work to be preformed in the Lab:
Set up the SONARCIRCUIT.BDF file. Properly configure the LPM_CLSHIFT block. Create a ModelSim simulation and verify the SONAR Circuit.
Set up the PROCESSOR.BDF file; save and compile it.
Set up the SONARPROJECT1.BDF file; save, compile, and simulate it by using ModelSim.
Set up, save, and compile the SONARPROJECT2.BDF file for testing at a sensor station in the lab.
Note:
Logic analyzer measurements will not be performed. You will use the simulation results to verify functionality before the final testing and verification of the design at the sensor test station.
ECE M. A. Jupina, VU, 2013

53. Design Verification at the Sensor Test Station
Bring your laptop to the sensor test station.
Start the Altera QUARTUS II software.
Go to PROGRAMMER and add your SONARPROJECT2.SOF file.
Test your design by walking back and forth two to seven feet in front of the sensor. What happens at 8 feet from the sensor?
Have either the instructor or TA verify the operation of your sonar sensor design.
Hand-in a print-out of the SONARPROJECT2.BDF file.
Before adding your SOF to the Programmer setup, delete the previously used SOF file if one exists.
Note: The Altera Board will be reset (powered off then on) after each test.
ECE M. A. Jupina, VU, 2013

54. Design Project: “Sonic Tape Measure”
Design and implement a sonic sensor system that measures distances in the units of either centimeters or inches at distances greater than ~2 feet from the sensor and calculates velocities in units of cm/s or inch/s. Your system must be able to measure the distance of an object from the sensor at least 10 feet away within  1 inch or  3 cm of accuracy.
ECE M. A. Jupina, VU, 2013

55. Design Project: “Sonic Tape Measure”
2. You will need to increase the word size (> 4 bits) in the processor block. You are to redesign the sonar circuit block in the prior sonar sensor project example. You can change the system clock frequency (see the note below and the following slide), the divider circuit, the counter circuit, etc to achieve your new system implementation. The seven segment displays can be used in whatever fashion you would like to display the distance measured and the calculated velocity. For example, the seven segment displays can display a base 10 or hex value indicating the total inches or centimeters measured, or the one seven segment display can indicate feet (in hex) and the second display can indicate inches (in hex).
Note: for the clk div block given to you, the frequencies derived from the 50 MHz signal are 1 MHz, 100 KHz, 10 KHz, 1 KHz, 100 Hz, 10 Hz and 1 Hz. Divide-by-50 and Divide-by-10 process blocks of VHDL code are used to generate these various frequencies. You can create any frequency required by your design by simply creating your own Divide-by-X block that can then be used with the given clk div block or can be used separately to generate a specific frequency derived from the 50 MHz onboard oscillator (see the following slide where a 25 MHz signal is divided down to a 720 KHz signal).
Instead of a binary (2^N) counter, a BCD counter (sections and of the text) may be useful in your design to display the measured value results directly on the seven segment displays for example. For the calculation of velocity, a BCD Adder (subtraction operation) could then be implemented (see section of the textbook).
ECE M. A. Jupina, VU, 2013

56. Divide-by-35 Circuit to Generate a 720 KHz Signal
Input: 25 MHz crystal oscillator signal
Output: 720 KHz signal
ECE M. A. Jupina, VU, 2013

57. Design Project Deliverables
Each group will hand-in a design proposal (due date TBA). In the design proposal (60% of the project grade), document all possible designs considered and then the final design (state why this design was chosen). Also, document contributions from each team member.
Each group will simulate their design to demonstrate functionality. Each group will demonstrate their design to the course instructor at the sensor test station (40% of the project grade). What is your measurement accuracy?
ECE M. A. Jupina, VU, 2013