1. NTU ARM Lab. Lab. 5 Memory Controller 指導教授 : 吳安宇 教授 學生 : 李源華 R91921062 鍾慶諺 R91522801 陳宗裕 P91921001

2. Lab. 5 Memory Controller Memory Map of ARM

3. Bug This program does the following tasks: 1. Backup the data in the SSRAM at locations 0x30000 to 0x38000 range to the SDRAM at locations 0x80000000 to 0x80008000. 2. Write values to the SSRAM at locations 0x30000 to 0x38000. 3. Verify the values in the SSRAM at locations 0x30000 to 0x38000. 4. Restore the backup data back to their original locations. printf ("Writing...\n"); for (i=0;i<0x8000;i+=4) { SSRAM_PTR = (unsigned int *) i ; *SSRAM_PTR = i; } printf ("Verifying...\n"); for (i=0x0;i<0x8000;i+=4) { SSRAM_PTR = (unsigned int *) i ; if (*SSRAM_PTR != i) { printf ("SSRAM W/R test error!!\n"); printf ("Error address>> %x\n",i); SSRAM_test_error = 1; Getchar (); } (i+0x30000)

4. Code Size of ARM

5. Code Size of Thumb

6. Core Module – Block Diagram

7. Processor write to System Bus

8. Processor read from System Bus

9. System Bus

10. Philips MP3 SOC – SAA7750EL

11. MP3 Player – SAA7750EL

12. How many guys ? If we have 1 IC designer, we should hire 4 Firmware/Software designers. Firmware/Software is very important in SOC Design. ex. SAA7750EL MP3 Player/ Ali DVD Chip Set software is not ready tile now. Taiwan IC Design house always do not follow this rule. So some system design houses have benefit ……hahhaha

13. Memory Types NAND Flash : a sequential access device appropriate for mass storage applications (song files of MP3…) NOR Flash(linear Flash) : a random access device appropriate for code storage applications SDRAM : Data process

14. Memory Controller AHB Wrapper (Memory Controller) SDRAM AHB Wrapper (Memory Controller) FLASH

15. FPGA/CPLD Configuration Configuration mode In configuration mode the debuggable devices are still accessible and, in addition, all FPGAs and PLDs in the system are added into the scan chain. This allows the board to be configured or upgraded in the field using Multi-ICE or other JTAG debugging equipment. To select configuration mode, fit a jumper to the CONFIG link on the core module at the top of the stack (see Figure 3-11 on page 3-23). This has the effect of pulling the nCFGEN signal LOW, illuminating the CFG LED (yellow) on each module in the stack, and rerouting the JTAG scan path. The LED provides a warning that the development system is in the configuration mode. From 3-26: DUI0126B_CM7TDMI_UG.pdf

16. FPGA/CPLD Configuration

17. Reference 1.ARM Core Module --- Core Module DUI0126B_CM7TDMI_UG.pdf 2.SDRAM Interface in Verilog --- Lattice Application Note re1007 3.NAND Flash interface in Verilog --- Xilinx Application Note XAPP354