1. Update on the Design Implementation Methodology for the 130nm process Microelecronics User Group meeting TWEPP 2010 – Aachen Sandro Bonacini CERN PH/ESE sandro.bonacini@cern.ch

2. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Motivation Mixed Signal Design flow methodology  Open Access based Implementation of Digital-On-Top ASICs  Script based flow Using the IBM 130 nm standard cell library

3. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Design flow components Tools  Virtuoso 6.1.3 (OA based)  SOC Encounter 8.1 (velocity)  Conformal 8.1  EXT 8.1.4 (QRC)  Assura 3.2  Calibre 2009.3 Design Kits  IBM CMOS8RF DM design kit V1.7 3 thin, 2 thick, 3 RF metals.  IBM CMOS8RF LM design kit V1.7 6 thin, 2 thick metals.

4. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Enhancements Digital library  I/O pads Implement missing Cadence/Virtuoso views  Functional and symbol views for simulation Fixed existing views  Pin mismatches of power pads  Abstract power pin width  Layout fixes New corner cells with 45 degrees bend  Standard cells New filler cells conforming to PC & RX pattern density rules New double vias for denser routing / better yield

5. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Enhancements Implementation flow  Added support for multiple power domains Analog, digital, …  Support for P&R of mixed signal ASICs and third-party IP blocks  Better integration between Virtuoso and Encounter Automatic final netlist import into Virtuoso  Automated physical verification DRC and LVS  Other fixes Scan chain reordering Antenna rule definition for Encounter Two-steps routing for DM metal stack to avoid antenna violations  1 st pass on 3 metals (only thin)  2 nd pass on 5 metals (thin+thick)

6. “Digital on Top” Design Flow 30/3/10 Kostas.Kloukinas@cern.ch 6 SOC_Encounter Chip Design SOC_Encounter Chip Design Virtuoso Analog Block Creation Virtuoso Analog Block Creation

7. Mixed-signal example design  Analog IP block: DAC  Digital IP block: SRAM  Digital block: I2C slave Synthesizable RTL code Triple Module Redundancy  Two separate power supplies Analog, digital 30/3/10 Kostas.Kloukinas@cern.ch 7 A realistic example of a Mixed Signal ASIC to demonstrate the design flow:

8. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Synthesis: RTL Compiler [rc] Timing constraints:  Clock definitions  Input delays, fanout, transition, etc.  Output load, etc.

9. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Design import: Encounter Reference design used in the AMS workshop:  I2C slave connected to SRAM DAC (with separate analog power supply) registers DAC SRAM

10. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Floorplanning & power routing Define  Chip/core size  target area utilization  I/O placement  module placement in case of TMR or other special constraints Power planning/routing  Core/block rings and stripes DACSRAM

11. Power/ground connections Placement Tap cells Standard cells Scan-chain reordering

12. Multiple power domains Analog & digital blocks  Separate power supplies.  Insertion of Power Breaker peripheral pads. DAC SRAM

13. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Clock tree synthesis & signal routing Clock tree synthesis Routing on thin metals Routing on all metals

14. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch DFM: Antenna fix Re-routes long nets Inserts tie-down diodes

15. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Via optimization

16. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Cells & metal fill

17. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Back to Virtuoso ! ASIC design is present in Virtuoso.  Scripts take care of changing abstracts into real layouts  Automatic import of netlist DAC SRAM

18. Calibre DRC – Assura LVS

19. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Thank you… Implementation of digital-on-top mixed signal ASICs  Using the IBM 130 nm standard cell library  Defined methodology compatible with mixed signal design flows  Presented in the AMS courses Future plans  Add signal integrity checks Celtic  Automate additional DRC checks (ortho/grid, …)