1. 1 PCI Express Analyzer המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

2. 2 הטכניון - מכון טכנולוגי לישראל Technion - Israel institute of technology Final Presentation Samuel Amir, Danny Volkind Mr. Orbach Mony Analyzer Core

3. 3 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Agenda PCI - Express – Reminder Link and Lane Training - Overview Project Goals Project features and capabilities PCI-Express Generator - Brief

4. 4 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Agenda (cont.) Project Block Diagram Demonstration Future Improvement Procedures

5. 5 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory PCI - Express Reminder

6. 6 PCI-Express Topology Ref. Clock Device A Device B TX+ TX- RX+ RX- TX+ TX- RX- RX+ המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Differential Dual Simplex Speeds of 2.5Gb/sec

7. 7 Packet Formation Packet formation reflects layered architecture. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Transaction Data Link Physical Transaction Layer Data Header Data Link Layer CRC Sequence Number Physical Layer Frame

8. 8 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 8/10b conversion (4.2.1) 8b/10b Encoded Byte Value Byte Value 00H Convert each byte to a 10bit character according to a pre- defined table. Extra characters are used as control characters or not used. Embedded clocking-> No need to add clock traces. Error detection (running disparity). DC balancing Reduces ISI.

9. 9 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory PCI Express scrambling (4.2.3) Assures no constant pattern is transmitted. Spread the energy transmitted in one frequency to different frequencies-> reduces EMI! (and gets FCC approval) Only data characters are encoded. Encoding is done using a linear feedback shift register. Decoding is done using the same process at the receiver side.

10. 10 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Frequency Mismatch (4.2.7) How does the protocol cope with the fact that each device is feed by a different clock source? Ref. Clock Device A Device B TX+ TX- RX+ RX- TX+ TX- RX- RX+

11. 11 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Frequency Mismatch (4.2.7) Input @ 2501MHz Output @ 2500MHz Input Shift Register is filling up faster than it is emptied! Input @ 2500MHz Output @ 2501MHz Input Shift Register is emptied faster than it is filled! If we take 600ppm difference between clocks, the transmitter and receiver clocks can shift one clock every 1666 clocks!

12. 12 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Frequency Mismatch-Solution The protocol issues a SKIP ordered set that can be skipped so that the input shift register can be partially cleared! The SKIP ordered sets insertion time as dictated by the protocol is between 1180 and 1538 symbol times. Calculated allowed deviance : ± 300ppm ! This is known as “clock tolerance compensation mechanism”.

13. 13 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Link & Lane Training

14. 14 Link and Lane Training המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Lane - a single set of differential RX TX pairs Link - a collection of lanes connecting two PCI-Express Devices. x1 Lane wide Link

15. 15 Link and Lane Training (cont) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Training - a process aimed at turning a collection of available lanes into a properly functioning link. Elements established during training : Physical Level SERDES lock. Symbol alignment. Link Level  link configuration Link data rate Link width Etc.

16. 16 Link and Lane Training (cont) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

17. 17 Training Ordered Sets המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Group of 16 symbols. Used During Polling State (TS1,TS2) Establish alignment Exchange Physical layer parameters Not scrambled!

18. 18 Training Ordered Sets (cont) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory TS1

19. 19 Fast Training Sequence המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Used to re-establish bit and symbol lock when transitioning out of the LO power management state. FTS pattern

20. 20 Skipped Ordered Set (CTC) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Compensate for differences in frequencies between bit rates at two devices sharing a mutual Link (Clock Tolerance Compensation) Skipped Ordered Set pattern

21. 21 Electrical Idle המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Steady state condition Transmitter differential pair held at fixed value Must remain at this state at least 20nsec Must attempt to detect a receiver within 100msec

22. 22 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory DLLP packet DLLP Contents 4byte CRC2byte Data Link Layer Frame1byte Frame1byte Physical Layer

23. 23 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory TLP packet Transaction Layer Data 0-4Kbyte Header 12/16byte Data Link Layer LCRC4byte Sequence#2byte Physical Layer Frame1byte Frame1byte

24. 24 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Packet Header Fmt Address/Routing Type Requestor ID Rsrv Traffic Class LengthAttrTag 16/12Byte Rsrv Byte Enables Data Payload Indicator and 16/12B header flag Memory, I/O, Config, Message; Request Message; Request or Completion or Completion Bus#, Device#, Function#, Virtual Channel Support TransactionTagReserved for future expansionAttributes:Snoop,Ordering First DW BE; Last DW BE Requested Length or Payload Size Header Transaction Layer Data Data Link Layer CRC Sequence Number Physical Layer Frame

25. 25 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Project Goals

26. 26 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Project Goal Overview PCI-Express packets capturing at wire speed of 2.5Gbps Selective filtering – work modes TLP analysis – header based filtering Simple register based user interface RS232 accessible.

27. 27 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Project Features & Capabilities

28. 28 Project features המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Receiving PCIe communication at 2.5 Gbps. Full line synchronization capability according to PCIe spec. Handling of realignment and clock tolerance compensation events on the fly. Invalid symbol filtering.

29. 29 Project features (cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Detection of and field extraction for all PCIe training sequences. Selective descrambling of the received data. Accumulative user-controlled counters for statistic purposes. Data stream marking and preliminary analysis.

30. 30 Projects features (cont.) 6 Available work modes: Wire Speed Capture. Capture TS1 / TS2 Capture DLLP Capture TLP Selective TLP capture המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

31. 31 Projects features (cont.) TLP filtering versatility: המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory TLP Type field5 Bit TLP format field2 Bit TLP Traffic Class3 Bit TLP length10 Bit TLP Attribute2 Bit TLP Tag8 Bit TLP Byte Enables or Message8 Bit TLP Sequence num12 Bit TLP Bus num8 Bit TLP device number5 Bit TLP function number3 Bit TLP poisoned packet1 Bit TLP Type field Mask5 Bit TLP format field Mask2 Bit TLP Traffic Class Mask3 Bit TLP length Mask10 Bit TLP Attribute Mask2 Bit TLP Tag Mask8 Bit TLP Byte Enables or Message Mask8 Bit TLP Sequence num Mask12 Bit TLP Bus num Mask8 Bit TLP device number Mask5 Bit TLP function number Mask3 Bit TLP poisoned packet Mask1 Bit

32. 32 Project features (cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Storage Fully user controlled dynamically allocated 16K x 32 memory. Captured data is saved with preliminary analysis. Bursts and capture events are separated allowing selective extraction.

33. 33 Project features (cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory LCD Interface Built-in LCD micro-controller implementation. 1 Kbyte user memory for display commands. Display file can be loaded on the fly.

34. 34 Project features (cont.) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory User Interface RS232 serial link operating at 115.2Kbps. Simple comm. protocol implementation allowing read and write commands accessing 32bit address space with 16bit data. All the core features are accessible.

35. 35 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Generator - Overview Capable of generating all PCIe traffic. Fully user-controlled. PCIe compatible including clock tolerance compensation simulation. Can be set to continuous or single shot mode.

36. 36 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Generator - Overview

37. 37 Basic Block Diagram Gigabit Receiver 1 1 Decryption Module 2 Wrap Filter 3 Packet Filter 4 MSU Control 5 Link Assessment 6 2 34 5 6 Memory Controller 7 Central Controller 8 7 8 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Physical Transaction Physical Data Link Transaction Physical Data Link

38. 38 Top Level המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

39. 39 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Project Block Diagram

40. 40 PDM – LFSR המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 8 bit values generated by LFSR for repeated data value of 0

41. 41 PDM – LFSR (cont) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Scrambling spectral power distribution for repeated data value of 0

42. 42 PDM – LFSR (cont) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

43. 43 PDM – LFSR (cont) המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

44. 44 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Demonstration Analyzer Completion Packet CRC Sequence Number Frame Request Packet CRC Sequence Number Frame Device A Device B

45. 45 Future Developments המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Additional functions. User interface development. Open Code flexibility opens the door for development

46. 46 Closing Words Thank You ! המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

47. 47 Additional information Certain images adopted from PCI-SIG PCI Express™ Architectural Overview Presented at the 2002 PCI-SIG Developers Conference and Intel Developers Forum, Fall 2001. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

48. 48 Project Development Process High Speed Communication Fundamentals Semester A Final Concept Requirements Doc PCI Express Architecture Concepts market survey Current Available Products Existing Infrastructure Constructing Analyzer Core Building Blocks Semester B Analyzer Core Development report Debugging & Testing Each block Final Core Integration המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory