1. Day 16: October 6, 2014 Inverter Performance
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 16: October 6, 2014
Inverter Performance
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2. Previously Delay as RC-charging Transistor Capacitance Drive Current
As a function of geometry (W/L)
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3. Today t-model Sizing Large Fanout Capacitance Revisited Miller Effect
Parallel Gate Capacitance
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4. Transistor Sizing What happens to Ids as a function of W?
What happens to Cg as a function of W?
Conclude: faster transistors present more load on their inputs
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5. First Order Delay R0 = Resistance of minimum size NMOS device
C0 = gate capacitance of minimum size NMOS device
Rdrive = R0/W
Cg = WC0
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6. First Order Delay (alt view)
I0 = Ids of minimum size NMOS device
C0 = gate capacitance of minimum size NMOS device
Idrive = WI0
Cg = WC0
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7. t model All delays are RC delays (CV/I delays)
Always have an R0C0 term (C/I term)
t = R0C0 (equivalently C0/I0)
Express all delays in t units
Like l units for measurement
Separate delay into
Technology dependent term t = R0C0
Technology independent term
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8. Inverter Sizing
What is the impact of the delay on the middle inverter if double size of all the transistors?
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9. How Size How size to equalize Rise and Fall?
mn=500cm2/Vs, mp=200cm2/Vs
When velocity saturated
Rdrive=R0/2 (Idrive=2I0)
Not velocity saturated Ids=(mCOX/2)(W/L)(Vgs-VTH)2
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10. SPICE Simulation
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11. SPICE Simulation 22nm
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12. Worst Case Delay Largest R Rdrive = max(Rpullup,Rpulldown)
If equalize Rpullup and Rpulldown
Rdrive = Rpullup=Rpulldown
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13. Equalizing Delay For simplicity, for today Assume Wp=Wn equalizes Ids
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14. Multistage Delay Total delay = sum of stage delays What is delay here?
From (P1,N1) to final capacitive load
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15. Large Fanout What is delay if must drive fanout=100?
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16. What Delay?
What is delay here?
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17. How Size How size transistors to minimize delay?
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18. Optimizing Delay = 2Wmid/1 + 200/Wmid How minimize?
D(Delay)/D(Wmid) = 0
2 – 200/(Wmid)2=0
Wmid=sqrt(100) = 10
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19. Delay?
Delay at optimal Wmid?
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20. Try again
What is the delay here?
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21. …and Again
Delay here?
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22. Lesson Don’t drive large fanout with a single stage
Must scale up over a number of stages
…but not too many
Exact number will be technology dependent
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23. Charge on Capacitors
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24. Questions What is DQ when switched? Equivalent Capacitance?
Contribution from each transistor?
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25. Gate-Drain Capacitance
What is the voltage across Vin—V2
When Vin=Vdd
When Vin=Gnd
What is DV across Vin—V2 when Vin switches from Vdd to Gnd?
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26. Miller Effect For an inverting gate
Capacitance between input and output must swing 2 Vhigh
Or…acts as double-sized capacitor
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27. Ideas First order delay reason in t=R0C0 units
Equivalently (C0/I0) units
Scaling everything up doesn’t help
Drive large capacitive loads in stages
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28. FPGA Architecture and Design
Admin
HW5 due Tuesday
Talk Today at 2pm in Towne 337
Mike Hutton (Altera)
FPGA Architecture and Design
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