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2. Digital cmos.2 10/15 Figure 10.1 Digital IC technologies and logic-circuit families. Digital IC Technologies CMOS & Pass Transistor Logic dominate

3. Digital cmos.3 10/15 Why CMOS Advantages Virtually, no DC power consumed No DC path between power and ground Excellent noise margins (VOL=0, VOH=VDD) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pMOS size larger to achieve electrical symmetry

4. Digital cmos.4 10/15 Figure 4.53 The CMOS inverter. Digital CMOS Inverter

5. Digital cmos.5 10/15 Figure 4.54 Operation of the CMOS inverter when v I is high: (a) circuit with v I = V DD (logic-1 level, or V OH ); (b) graphical construction to determine the operating point; (c) equivalent circuit. CMOS Inverter Operation; Vin = Hi Equivalent circuit Hi Lo

6. Digital cmos.6 10/15 Figure 4.55 Operation of the CMOS inverter when v I is low: (a) circuit with v I = 0 V (logic-0 level, or V OL ); (b) graphical construction to determine the operating point; (c) equivalent circuit. CMOS Inverter Operation; Vin = Lo Hi Lo

7. Digital cmos.7 10/15 Figure 4.56 The voltage transfer characteristic of the CMOS inverter. CMOS Inverter Transfer characteristic V IL = highest input voltage still interpreted as an input low (resulting in out = Hi) V IH = lowest input voltage still interpreted as an input Hi (resulting in out = lo) NM H = V OH – V IH NML= V IL - V OL

8. Digital cmos.8 10/15 Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors. CMOS Logic gates ? Pullup(s) & pulldown(s)

9. Digital cmos.9 10/15 Figure 10.9 Examples of pull-down networks. CMOS Logic gate pulldown Examples

10. Digital cmos.10 10/15 Figure 10.10 Examples of pull-up networks. CMOS Logic gate pullup Examples

11. Digital cmos.11 10/15 Figure 10.11 Usual and alternative circuit symbols for MOSFETs. CMOS Transistor Symbols

12. Digital cmos.12 10/15 CMOS Logic gate Example 1 ?

13. Digital cmos.13 10/15 CMOS Logic gate Example 2 ?

14. Digital cmos.14 10/15 CMOS Logic gate Example 3

15. Digital cmos.15 10/15 CMOS Logic gate Example 4 Y = ?

16. Digital cmos.16 10/15 Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion. CMOS Inverter Representation Can be represented as Simple switch

17. Digital cmos.17 10/15 Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through Q N ; (d) equivalent circuit during the capacitor discharge. CMOS Inverter Dynamic Operation Input Output

18. Digital cmos.18 10/15 Figure 4.58 The current in the CMOS inverter versus the input voltage. CMOS Inverter Current VS voltage

19. Digital cmos.19 10/15 Figure 10.3 Definitions of propagation delays and switching times of the logic inverter. CMOS Inverter - Propagation delays t PHL = Hi to lo t PLH = lo to Hi Input t r = rise time t f = fall time Output

20. Digital cmos.20 10/15 Figure 10.6 Circuit for analyzing the propagation delay of the inverter formed by Q 1 and Q 2, which is driving an identical inverter formed by Q 3 and Q 4. CMOS Inverter Source of prop. delays

21. Digital cmos.21 10/15 Figure 10.7 Equivalent circuits for determining the propagation delays (a) t PHL and (b) t PLH of the inverter. CMOS Inverter Hi to Lo prop. Delay analysis t PHL t PLH Lo to Hi

22. Digital cmos.22 10/15 Music for your ears

23. Digital cmos.23 10/15 Musique 101

24. Digital cmos.24 10/15 Figure 10.23 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C). Pass Transistor Logic PTL

25. Digital cmos.25 10/15 Figure 10.24 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate. PTL Switch NMOS switch CMOS switch Aka transmission gate

26. Digital cmos.26 10/15 Figure 10.25 A basic design requirement of PTL circuits is that every node have, at all times, a low-resistance path to either ground or V DD. Such a path does not exist in (a) when B is low and S 1 is open. It is provided in (b) through switch S 2. PTL – Need path to ground Or V DD For proper logic voltage levels

27. Digital cmos.27 10/15 Figure 10.26 Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for the case with the switch closed ( v C is high) and the input going high ( v I = V DD ). PTL Switch closed

28. Digital cmos.28 10/15 Figure 10.27 Operation of the NMOS switch as the input goes low ( v I = 0 V). Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles comparison to the circuit in Fig. 10.26. PTL Switch Open

29. Digital cmos.29 10/15 Figure 10.29 Operation of the transmission gate as a switch in PTL circuits with (a) v I high and (b) v I low. Transmission gate in action

30. Digital cmos.30 10/15 Figure 10.30 Realization of a ……??????………….multiplexer using pass-transistor logic. Transmission gate in action Multiplexer ?

31. Digital cmos.31 10/15 Figure 10.31 Realization of the ……. function using pass-transistor logic. Transmission gate in action Gate ?

32. Digital cmos.32 10/15 Figure 10.32 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated. Transmission gate in action Gate ?

33. Digital cmos.33 10/15 Figure 10.28 The use of transistor Q R, connected in a feedback loop around the CMOS inverter, to restore the V OH level, produced by Q 1, to V DD. Transmission gate (NMOS) drops Vt Across switch PMOS pullup can be used to restore V

34. Digital cmos.34 10/15 Barrel Shifter, used in ICs Shift ……???…. using one transistor per switch

35. Digital cmos.35 10/15 Barrel Shifter, used in ICs Shift ……???…. using one transistor per switch D3 D2 D1 D0 A6 A5 A4 A3A2A1A0 SR0SR1SR2SR3

36. Digital cmos.36 10/15 Barrel Shifter, used in ICs Shift ……Left ???…. Exercise

37. Digital cmos.37 10/15 Barrel Shifter, used in ICs Shift ……Left ???…. Exercise D3 D2 D1 D0 A5 A4 A3 A2A1A0 SR0SR1SR2 SL ?

38. Digital cmos.38 10/15 Figure P10.36 How many transistors in each gate implementation ?

39. Digital cmos.39 10/15 Figure 10.19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter. Other Inverter Implementations All NMOS - Not very popular -- FYI (a) pseudo-NMOS logic inverter.(b) The enhancement-load NMOS inverter. © The depletion-load NMOS inverter.

40. Digital cmos.40 10/15 Figure 10.38 Capture schematic of the CMOS inverter in Example 10.5. Pspice Simulation example …. later

41. Digital cmos.41 10/15 CMOS Inverter Netlist generating inverter transfer curve * here's the inverter netlist declaration * mosfet: mxx drain gate source substrate model length width m1 OUT IN VDD VDD CMOSP l=.5u w=2u m2 OUT IN GND GND CMOSN l=.5u w=2u * constant voltage source: vxx node1 node2 voltage VDD VDD GND 5 * Define a voltage source connected to Vin and initialize voltage to 0 Vin IN Gnd 0 * Sweep Vin from 0 to 5 volts in increments of.1 volt.DC Vin 0 5.1 * Print the voltage at OUT.print dc v(OUT).end