1. Shih-Fan, Peng 2013 IEE5008 –Autumn 2013 Memory Systems DRAM Controller for Video Application Shih-Fan, Peng Department of Electronics Engineering National Chiao Tung University hankban@hotmail.com

2. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Outline Introduction Traditional Controller DRAM Memory Controller for Video Application Conclusion Reference 2

3. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng DRAM WORK 3

4. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng DRAM WORK(cont.) 4

5. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng DRAM Organization 5

6. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Introduction What is DRAM Memory Controller? Manage the movement of data in and out of DRAM devices Error detection and correction 6

7. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Abstract DRAM Memory Controller 7

8. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Address Mapping (Translation) Translation a given physical address in to indices in a DRAM memory system Channel ID, rank ID, bank ID, row ID, column ID Mapping scheme is often coupled to the row-buffer- management policy Ex: memory request sequence Mapping to different rows of the same bank Mapping to different rows of different bank 8

9. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Write caching Write requests are typically non-critical in terms of latency Defer write requests and allow read requests to proceed ahead But sometime it is not good Read requests must be checked against the address of cached writes Controller must ensure the correctness of memory- access order 9

10. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Request Queue Organizations Place the commands into single queue or multiple queue Prioritize commands on many different factor Priority of the request, availability of resources to a given queue, bank address of the request, age of request….. Ex: per-bank queuing organization Base on bank address 10

11. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Refresh Management DRAM must be refreshed to ensure the integrity of the data Ex: pseudo-static DRAM Temperature-compensated self-refresh is used If request collides with refresh action, assert a wait signal used in low frequency Separate refresh to each bank 11

12. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Method: Optimized the data arrangement Minimize the number of overhead cycles needed for row-activations Consider the feature of SDRAM and memory- access patterns of video-processing application Video-processing algorithms usually uses multi- dimensional arrays and nested loops 12

13. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng 13 Timing diagram of two consecutive read cycle

14. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Row changes for logical array with (1,128) window Consider a 2-D array of 8X8 data Cause seven row changes→more latency and power consumption 14

15. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Row changes for logical array with (8,16) window A logical array is portioned into a set of rectangles called windows Each window is stored in a row of SDRAM 15

16. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Condition for Minimal Overhead Cycles Condition: two banks, the horizontal size of windows is greater than the loop bound 16

17. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Method: History-based predictive approach(HDTV) What if the row address differs from the previous one? Page miss Additional cycles cannot be hidden What can do for it? Statically schedule the address sequence Control the memory operation mode But if it is irregular? 17

18. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng History-based predictive approach If t rp can be overlapped to burst accesses or data transfer between the memory controller and the processor Effective latency=t RCD + t CL Use the past history of memory reference Predict next access (built a two-bit counter for each row) If history predicts to same row  Bank remain in row active state If not  Change to idle state 18

19. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Two-bit saturated up/down counter(per- row) SH,WH→auto-precharge is not issued SM,WM→auto-precharge is issued 19

20. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Method: Burst Terminates Burst and Anticipative Row Activation In video application, most bandwidth is consumed by 2-D block data Block data may consist of several non-sequential accesses Data length is inconstant 20

21. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Organization of Address Bus Allocate and address space larger than the physical address Seamless transfer Mode Control Information (MCI) to memory controller Burst access operation is pre-calculated by embedded address generator(EAG) MCI=Mode Select (MS)& Stride control (SC) 21

22. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Organization of Address Bus 22

23. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng BTB and ARA 23

24. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Conclusion Optimize data arrangement Select the suitable window size History-based predictive approach Predict the successive memory access BTB and ARA Provide the parallel access of different banks 24

25. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng Reference [1] H. Kim and I. C. Park, “High Performance and Low Power Memory Interface Architecture for Video Processing Applications”, IEEE Transaction on Circuits and Systems for Video Technology, vol.11, pp. 1160 – 1170, 2001. [2] J. Zhu, L. Hou, W. Wu, R. Wang, C. Huang, and J. Li, “High performance synchronous DRAMs controller in H.264 HDTV decoder,” in Proc. International Conference on Solid State and Integrated Circuits Technology, vol. 3, pp. 1621 – 1624, 2004. [3] S. I. Park, Y. Yi, and I. C Park, “High Performance Memory Mode Control for HDTV Decoders,” IEEE Transactions on Consumer Electronics, vol. 49, no. 4, pp. 1348 – 1353, November, 2003. [4] H-Y Kang, K-A Jeong, J-Y Bae, Y-S Lee, and S-H Lee, “MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller,” in Proc. ISCAS, vol. 2, pp. 145 – 148, May, 2004. [5] K. B. Lee, T. C. Lin, and C. W Jen, “An Efficient Qual ity- Aware Memory Controller for Multimedia Platform SoC,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 5, pp. 620 – 633, May 2005. [6]G. Hyun, Y. Jin, J. Jung, S. Kim, “A Synchronous DRAM Controller of an H.264/AVC Encoder” International SoC Design Conference, Vol. 02, pp. II-113- II-116,2008 [7]Textbook: Memory Systems: Cache, DRAM, Disk chapter 13 25

26. NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng 26 Thank you for your listening