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Digital Integrated Circuits A Design Perspective

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Presentation on theme: "Digital Integrated Circuits A Design Perspective"— Presentation transcript:

1 Digital Integrated Circuits A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002

2 A model for manual analysis

3 Simulation versus Model (NMOS)
The square-law model doesn’t match well with simulations Only fits for low Vgs, low Vds (low E-field) conditions Chris Kim

4 Simulation versus Model (PMOS)
Not as bad as the NMOS device Still large discrepancies at high E-field conditions Chris Kim

5 Simulation versus Model (Ids vs. Vgs)
Saturation current does not increase quadratically The simulated curves looks like a straight line Main reason for discrepancy: velocity saturation Chris Kim

6 Velocity Saturation E-fields have gone up as dimensions scale
Unfortunately, carrier velocity in silicon is limited Electron velocity saturates at a lower E-field than holes Mobility (μe=v/E) degrades at higher E-fields Simple piecewise linear model can be used Chris Kim

7 Velocity Saturation Modeled through a variable mobility
[Toh, Ko, Meyer, JSSC, 8/1988] Modeled through a variable mobility n=1 for PMOS, n=2 for NMOS To get an analytical expression, assume n=1 Chris Kim, Kia

8 Equate the two expressions to get
Velocity Saturation Plug it into the original current equation Equate the two expressions to get Chris Kim, Kia

9 Simulation versus Model
Model incorporating velocity saturation matches fairly well with simulation Chris Kim

10 Current-Voltage Relations The Deep-Submicron Era
-4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation Linear Relationship

11 Perspective I V Long-channel device V = V Short-channel device V V - V
GS DD Short-channel device V V - V V DSAT GS T DS

12 ID versus VGS linear quadratic quadratic Long Channel Short Channel
0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V GS (V) I D (A) 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) linear quadratic quadratic Long Channel Short Channel

13 ID versus VDS Resistive Saturation VDS = VGS - VT Long Channel
0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT -4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Long Channel Short Channel

14 A unified model for manual analysis
G B

15 Simple Model versus SPICE
0.5 1 1.5 2 2.5 x 10 -4 Velocity Saturated Linear Saturated VDSAT=VGT VDS=VDSAT VDS=VGT (A) I D V (V) DS

16 A PMOS Transistor Assume all variables negative! -2.5 -2 -1.5 -1 -0.5
-0.8 -0.6 -0.4 -0.2 x 10 -4 V DS (V) I D (A) VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! VGS = -2.5V

17 The Transistor as a Switch
Eq added by Kia

18 The Transistor as a Switch
Eq added by Kia

19 MOS Capacitances Dynamic Behavior

20 Dynamic Behavior of MOS Transistor

21 The Gate Capacitance x L Polysilicon gate Top view Gate-bulk overlap
d L Polysilicon gate Top view Gate-bulk overlap Source n + Drain W t ox n + Cross section L Gate oxide

22 Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off

23 Gate Capacitance Capacitance as a function of VGS
(with VDS = 0) Capacitance as a function of the degree of saturation

24 Diffusion Capacitance
Channel-stop implant N 1 A Side wall Source W N D Bottom x Side wall j Channel L S Substrate N A

25 Capacitances in 0.25 mm CMOS process


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