1. Refer to Chapter 15 in the reference book
The Cortex-M3 Embedded Systems: LM3S9B96 Microcontroller – Inter- Integrated Circuit (I2C) Interface
Refer to Chapter 15 in the reference book
“Stellaris® LM3S9B96 Microcontroller - DATA SHEET”

2. Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus :
bi-directional data transfer via a two-wire design: a serial data line SDA and a serial clock line SCL
interfaces to external I2C devices: serial memory, networking devices, LCDs, tone generators

3. Inter-Integrated Circuit (I2C) Interface
The LM3S9B96 microcontroller includes two I2C modules:
Supports both transmitting and receiving data as either a master or a slave
Four I2C modes: Master/Slave transmit/receive
Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
Master and slave interrupt generation
Master with arbitration and clock synchronization, multi-master support, and 7-bit addressing mode

4. Block Diagram

5. Functional Description
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers
The bus is considered idle when both lines are High
Every transaction on the I2C bus is nine bits long, i.e., 8 data bits (MSB first) and 1 single acknowledge bit
The number of bytes in one transfer is unrestricted
When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state
The data transfer continues when the receiver releases the clock SCL

6. I2C Bus Configuration
SCL Output
SDA Output
SCL Input
SDA Input

7. START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition
A Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition

8. Data Format with 7-Bit Address
After the START condition, a slave address is transmitted
The address is 7 bits long and followed by a direction bit (R/S bit in the I2C Master Slave Address (I2CMSA) register)
If R/S is cleared, a transmit operation (send)
If R/S is set, a request for data (receive)
A data transfer is always terminated by a STOP condition generated by the master
A master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition.

9. Data Format with 7-Bit Address
A zero in the R/S position of the first byte means that the master transmits (sends) data to the selected slave, and a one in this position means that the master receives data from the slave

10. Data Validity
The data on the SDA line must be stable during the high period of the clock
The data line can only change when SCL is Low

11. Acknowledge
All bus transactions have a required acknowledge clock cycle
During the acknowledge cycle, the transmitter (master or slave) releases the SDA line
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle
When a slave receiver does not ack the slave address, the master can generate a STOP condition and abort the current transfer.
When the master acting as a receiver, it is responsible for acknowledging each transfer made by the slave
The master receiver controls the number of bytes in the transfer by not generating an acknowledge on the last data byte; slave transmitter will give up the data line

12. Available Speed Modes
The I2C bus can run in either Standard mode (100 kbps) or Fast mode (400 kbps)
The selected mode should match the speed of the other I2C devices on the bus
The mode is selected by using a value in the I2C Master Timer Period (I2CMTPR) register
The I2C clock rate is determined by the parameters:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2CMTPR register

13. Available Speed Modes
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
For example: CLK_PRD = 50 ns, TIMER_PRD = 2, SCL_LP=6, SCL_HP=4
Therefore, the SCL frequency is : 1/SCL_PERIOD = 333 Khz

14. Interrupts
The I2C can generate interrupts when the following conditions are observed:
Master transaction completed
Master transaction error
Slave transaction received
Slave transaction requested
Stop condition on bus detected
Start condition on bus detected
The I2C master and I2C slave modules have separate interrupt signals
A module can generate interrupts for multiple conditions but only one single interrupt signal is sent to the interrupt controller

15. I2C Master Interrupts
When a transaction completes or when an error occurs during a transaction
To enable the I2C master interrupt, the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register must be set
When an interrupt condition is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur
The interrupt is cleared by writing a 1 to the IC bit in the I2C Master Interrupt Clear (I2CMICR) register
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register

16. I2C Slave Interrupts When data has been received or requested
This interrupt is enabled by setting the DATAIM bit in the in the I2C Slave Interrupt Mask (I2CSIMR) register
Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register
The interrupt is cleared by setting the DATAIC bit in the I2C Slave Interrupt Clear (I2CSICR) register
In addition, the slave module can generate an interrupt when a start and stop condition is detected (STARTIM and STOPIM bits in I2CSIMR)
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CMRIS) register

17. Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work
Set the LPBK bit in the I2C Master Configuration (I2CMCR) register
SDA and SCL signals from the master and slave modules are tied together

18. I2C Master Command Sequences

19. I2C Master Command Sequences

20. I2C Slave Command Sequences

21. Register Map The I2C’s base address: I2C Master 0: 0x4002.0000
I2C Slave 0: 0x
I2C Master 1: 0x
I2C Slave 1: 0x

22. I2C Master Slave Address (I2CMSA), offset 0x000
Set the slave address of this master and define the transmission direction

23. I2C Master Control/Status (I2CMCS), offset 0x004
When read, status register indicating the state of the I2C bus controller; when written, control register configuring the operation of the I2C bus controller

24. I2C Master Control/Status (I2CMCS), offset 0x004
When read, status register indicating the state of the I2C bus controller; when written, control register configuring the operation of the I2C bus controller

25. I2C Master Data (I2CMDR), offset 0x008
This register contains the data to be transmitted when in the Master Transmit state and the data received when in the Master Receive state

26. I2C Master Configuration (I2CMCR), offset 0x020
configures the mode (Master or Slave) and sets the interface for test mode loopback

27. I2C Slave Control/Status (I2CSCSR), offset 0x804
This register functions as a control register when written, and a status register when read.

28. I2C Slave Control/Status (I2CSCSR), offset 0x804
This register functions as a control register when written, and a status register when read.

29. Initialization and Configuration
The following example shows how to configure the I2C module to transmit a single byte as a master:
1. Enable the I2C clock by writing a value of 0x to the RCGC1 register in the System Control module
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module
3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register
4. Enable the I2C pins for Open Drain operation
5. Configure the PMCn fields in the GPIOPCTL register to assign the I2C signals to the appropriate
6. Initialize the I2C Master by writing the I2CMCR register with a value of 0x

31. Initialization and Configuration
7. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value:
(System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
= (20MHz/(2*(6+4)*100000))-1;
= 9
8. Specify the slave address of the master and that the next operation is a Transmit by writing the I2CMSA register with a value of 0x , which sets the slave address to 0x3B
9. Place data (byte) to be transmitted in the data register by writing the I2CMDR register with the desired data
10. Initiate a single byte transmit of the data from Master to Slave by writing the I2CMCS register with a value of 0x (STOP, START, RUN)
11. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has been cleared.

32. PCA9557: REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER

33. Reference
“REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS”

34. Chip Description and Key Features
8-bit I/O expander for I2C bus
I2C to parallel port expander
400-kHz fast I2C bus
3 hardware address pins allow for use of up to 8 devices on I2C
Noise filter on SCL/SDA inputs
General-purpose remote I/O expansion for most microcontroller families
At power on, the I/Os are configured as inputs
The I/Os can be programmed by I2C master to be as either inputs or outputs
Latched outputs with high current drive maximum capability for directly driving LEDs
Data for each input or output is kept in the corresponding input or output register
The polarity of the input port register can be inverted with the polarity inversion register

35. Package & Pins
Top-side marking: PD557

36. Logic Diagram

37. I2C Protocol Review
Two lines: the serial clock (SCL) and serial data (SDA)
Connected to a positive supply through a pull-up resistor
Communication is initiated by a master sending a start condition
A high-to-low transition on the SDA & the SCL input is high
After the start condition, the device address byte is sent
Most-significant bit (MSB) first
Followed by the data direction bit (R/W)
After receiving the valid address byte, the device having this address responds with an ACK
A low on the SDA during the high of the ACK-related clock pulse

38. I2C Protocol Review Cont.
Data transfer begins
Only one data bit is transferred during each clock pulse
Any number of data bytes can be transferred from the transmitter to the receiver
Each byte of eight bits is followed by one ACK bit
The transmitter must release the SDA line
The receiver must pull down the SDA line during the ACK clock pulse
Master will stop the transmission by issuing a stop condition
A low-to-high transition on the SDA & the SCL input is high

39. Device Address The address of the PCA9557 is shown as follows
R/~W: a high (1) indicates a read operation,
while a low (0) selects a write operation, from the perspective of the Master.

40. Control Register & Command Byte
After the successful ACK of the address type, the bus master sends a command byte that is stored in the control register in the PCA9557
Command bytes are used to specify the operation and the internal registers that will be affected

41. Input Port Register Reflects the incoming logic levels of the pins
All pins no matter whether a pin is an input or an output
The default value is determined by the externally applied logic level

42. Output Port Register
Shows the outgoing logic levels of the pins defined as outputs
Bit values in this register have no effect on pins defined as inputs
reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value

43. Polarity Inversion Register
Inverts the polarity of input pins
If a bit in this register is set, the corresponding port pin's polarity is inverted
If a bit in this register is cleared, the corresponding port pin's original polarity is retained

44. Configuration Register
Configures the directions of the I/O pins
If a bit in this register is set to 1, the corresponding port pin is enabled as an input
If a bit in this register is cleared, the corresponding port pin is enabled as an output

45. Write Operation

46. Write Operation

47. Read Operation

48. I2C on S700

49. Digital LED Tubes on S700