1. EE207: Digital Systems I, Semester I 2003/2004
25-Apr-17
EE207: Digital Systems I, Semester I 2003/2004
CHAPTER 6-i:
Programmable Logic Devices (PLDs)
Chapter 6-i: Programmable Logic Devices (Sections )

2. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Overview
Three-State Buffers
Programmable Logic Technologies
Read-Only Memory (ROM)
Programmable Logic Arrays (PLAs)
Programmable Array Logic (PAL)
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Chapter 6-i: Programmable Logic Devices ( )

3. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Three-State Buffers
Buffer output has 3 states: 0, 1, Z
Z stands for High-Impedance  Open circuit
EN = 0  out = Z (open circuit)
EN = 1  out = in (regular buffer) EN in
out X Z 1 EN in
out
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Chapter 6-i: Programmable Logic Devices ( )

4. Three-state buffer(BUF)/inverter(INV) symbolsEN EN in
out in
out
3-state BUF, EN high
3-state INV, EN high EN EN in
out in
out
3-state BUF, EN low
3-state INV, EN low
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Chapter 6-i: Programmable Logic Devices ( )

5. Multiplexed output lines using three-state buffers
Assume an output line that can receive data from either a system (circuit) A or a system B. A
If A = B  out = A = B
If A  B  a large enough current can be created, that causes excessive heating and could damage the circuit.
out B
wired logic
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Chapter 6-i: Programmable Logic Devices ( )

6. Multiplexed output lines using three-state buffers (cont.)
Solution: S A B
ENA
ENB
out 1 A B S
out 1 A B
out
ENA
ENB S A B
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Chapter 6-i: Programmable Logic Devices ( )

7. Programmable Logic Devices (PLDs)
Standard logic devices that can be programmed to implement any combinational logic circuit.
Standard  of regular structure
Programmed  refers to a hardware process used to specify the logic that a PLD implements
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Chapter 6-i: Programmable Logic Devices ( )

8. One major difference! Gate Symbols . . . . . .
Conventional AND gate symbol
Array Logic OR gate symbol
One major difference! a b c
F = 0 a F b c
F = a.c
F = a.b.c
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Chapter 6-i: Programmable Logic Devices ( )

9. Read-Only Memory (ROM)
Stores binary information permanently
Non-Volatile (info is kept even when power is turned off)
k inputs = specify the # of addresses available
n outputs = specify the size of data
ROM
2k x n k m
Block Diagram
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Chapter 6-i: Programmable Logic Devices ( )

10. Read-Only Memory (cont.)
Address
8x4 ROM
Example: k=3, n=4
There are 23=8 available addresses
4-bits are stored in each address 1 2 3 4 5 6 7 3 4
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Chapter 6-i: Programmable Logic Devices ( )

11. ROM construction: Example of an 25x8 ROM
Use a 5-to-32 decoder to generate the 32 addresses.
Use 8 OR gates, each can be programmed to be driven by any of the decoder outputs.
Programmable
logic. # of
interconnections is 25x8
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Chapter 6-i: Programmable Logic Devices ( )

12. Programming the ROM, i.e. load desired data at specified addresses
(in decimal) 1 2 3 28 29 30 31
ROM addresses
ROM data
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Chapter 6-i: Programmable Logic Devices ( )

13. Programming the ROM (cont.)
Example: Let I0I1I3I4 = (address 2). Then, output 2 of the
decoder will be 1, the remaining outputs will be 0, and ROM output
becomes A7A6A5A4A3A2A1A0 =
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Chapter 6-i: Programmable Logic Devices ( )

14. ROM-based circuit implementation
Given a 2kxn ROM, we can implement ANY combinational circuit with at most k inputs and at most n outputs.
Why?
k-to-2k decoder will generate all 2k possible minterms
Each of the OR gates must implement a m()
Each m() can be programmed
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Chapter 6-i: Programmable Logic Devices ( )

15. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Example
Find a ROM-based circuit implementation for:
f(a,b,c) = a’b’ + abc
g(a,b,c) = a’b’c’ + ab + bc
h(a,b,c) = a’b’ + c
Solution:
Express f(), g(), and h() in m() format (use truth tables)
Program the ROM based on the 3 m()’s
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Chapter 6-i: Programmable Logic Devices ( )

16. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Example (cont.)
There are 3 inputs and 3 outputs, thus we need a 8x3 ROM block.
f = m(0, 1, 7)
g = m(0, 3, 6, 7)
h = m(0, 1, 3, 5, 7) a 1 2 3 4 5 6 7
3-to-8 decoder b c f g h
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Chapter 6-i: Programmable Logic Devices ( )

17. Programmable Logic Arrays (PLAs)
Similar concept as in ROM, except that a PLA does not necessarily generate all possible minterms (ie. the decoder is not used).
More precisely, in PLAs both the AND and OR arrays can be programmed (in ROM, the AND array is fixed – the decoder – and only the OR array can be programmed).
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Chapter 6-i: Programmable Logic Devices ( )

18. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
PLA Example
f(a,b,c) = a’b’ + abc
g(a,b,c) = a’b’c’ + ab + bc
h(a,b,c) = c
PLAs can be more compact
implementations than ROMs,
since they can benefit from
minimizing the number
of products required to
implement a function
AND array
OR array
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Chapter 6-i: Programmable Logic Devices ( )

19. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Another PLA Example
Find a PLA-based circuit implementation for:
F1(A,B,C) = AB’ + AC + A’BC’
F2(A,B,C) = (AC + BC)’
Solution:
3 inputs, 2 outputs ( 2 OR gates)
4 distinct product terms (4 AND gates)
Use XOR array to find complements
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Chapter 6-i: Programmable Logic Devices ( )

20. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
PLA Example (cont.)
XOR array
F2’ F1
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Chapter 6-i: Programmable Logic Devices ( )

21. PLA Example (cont.) Tabular Form Specification
of interconnection programming
F1 = AB’+AC+A’BC’
F2 = AC+BC
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Chapter 6-i: Programmable Logic Devices ( )

22. Determining the size of a PLA
Given:
n inputs
p product terms
m outputs
PLA size is:
Gates: n INV (and maybe n BUF) + p ANDs + m ORs + m XORs
Programmable interconnections: 2np + pm + 2m
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Chapter 6-i: Programmable Logic Devices ( )

23. Programmable Array Logic (PAL)
OR plane (array) is fixed, AND plane can be programmed
Less flexible than PLA
# of product terms available per function (OR outputs) is limited
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Chapter 6-i: Programmable Logic Devices ( )

24. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
PAL Example
inputs
1st output
section
2nd output
section
Only functions with
at most four
products can be
implemented
3rd output
section
4th output
section
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Chapter 6-i: Programmable Logic Devices ( )

25. PAL-based circuit implementation
W = ABC + CD
X = ABC + ACD + ACD + BCD
Y = ACD + ACD + ABD
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Chapter 6-i: Programmable Logic Devices ( )

26. Can we implement more complex functions using PALs?
Yes, by allowing output lines to also serve as input lines in the AND plane.
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Chapter 6-i: Programmable Logic Devices ( )

27. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Example
Implement the combinational circuit described by the following equations, using a PAL with 4 inputs, 4 outputs, and 3-wide AND-OR structure.
W(A,B,C,D) = m(2,12,13)
X(A,B,C,D) = m(7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) = m(0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D) = m(1,2,8,12,13)
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Chapter 6-i: Programmable Logic Devices ( )

28. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Example (cont.)
Use function simplification techniques to derive:
W = ABC’+A’B’CD’
X = A+BCD
Y=A’B+CD+B’D’
Z=ABC’+A’B’CD’+AC’D’+A’B’C’D = W + AC’D’+A’B’C’D
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Chapter 6-i: Programmable Logic Devices ( )

29. Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)
Example (cont.)
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Chapter 6-i: Programmable Logic Devices ( )

30. Example (cont.) Tabular Form Specification
of interconnection programming
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Chapter 6-i: Programmable Logic Devices ( )