1. EE141 Combinational Circuits 1 Chapter 6 Designing Combinational Logic Circuits November 2002.

2. EE141 Combinational Circuits 2 Combinational vs. Sequential Logic CombinationalSequential Output = f ( In ) Output = f ( In, Previous In )

3. EE141 Combinational Circuits 3 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD orV ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

4. EE141 Combinational Circuits 4 Complementary CMOS Logic Style

5. EE141 Combinational Circuits 5 Static Complementary CMOS V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks … …

6. EE141 Combinational Circuits 6 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

7. EE141 Combinational Circuits 7 PMOS Transistors in Series/Parallel Connection

8. EE141 Combinational Circuits 8 Example Gate: NAND

9. EE141 Combinational Circuits 9 Example Gate: NOR

10. EE141 Combinational Circuits 10 Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

11. EE141 Combinational Circuits 11 Constructing a Complex Gate

12. EE141 Combinational Circuits 12 CMOS Properties  Full rail-to-rail swing; high noise margins  Logic levels not dependent upon the relative device sizes; ratioless  Always a path to Vdd or Gnd in steady state; low output impedance  Extremely high input resistance; nearly zero steady- state input current  No direct path steady state between power and ground; no static power dissipation  Propagation delay function of load capacitance and resistance of transistors

13. EE141 Combinational Circuits 13 Properties of Complementary CMOS Gates Snapshot 1. High noise margins: V OH andV OL are atV DD andGND, respectively. 2. No static power consumption: There never exists a direct path betweenV DD and V SS (GND) in steady-state mode. 3. Comparable rise and fall times: (under appropriate sizing conditions)

14. EE141 Combinational Circuits 14 Threshold Drops V DD V DD  0 PDN 0  V DD CLCL CLCL PUN V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D

15. EE141 Combinational Circuits 15 Switch Delay Model A R eq A RpRp A RpRp A RnRn CLCL A CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL NAND2 INV NOR2

16. EE141 Combinational Circuits 16 Input Pattern Effects on Delay  Delay is dependent on the pattern of inputs  Low to high transition  Both inputs go low –Delay is 0.69 R p /2 C L  One input goes low –Delay is 0.69 R p C L  High to low transition?  Both inputs go high –Delay is 0.69 2R n C L CLCL B RnRn A RpRp B RpRp A RnRn C int

17. EE141 Combinational Circuits 17 Delay Dependence on Input Patterns A=B=1  0 A=1, B=1  0 A=1  0, B=1 time [ps] Voltage [V] Input Data Pattern Delay (psec) A=B=0  1 67 A=1, B=0  1 64 A= 0  1, B=1 61 A=B=1  0 45 A=1, B=1  0 80 A= 1  0, B=1 81 NMOS = 0.5  m/0.25  m PMOS = 0.75  m/0.25  m C L = 100 fF

18. EE141 Combinational Circuits 18 Transistor Sizing CLCL B RnRn A RpRp B RpRp A RnRn C int B RpRp A RpRp A RnRn B RnRn CLCL 2222 22 1 1 4444

19. EE141 Combinational Circuits 19 Transistor Sizing a Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C 1 2 22 4 4 8 8 6 3 6 6

20. EE141 Combinational Circuits 20 Fan-In Considerations DCBA D C B A CLCL C3C3 C2C2 C1C1 Distributed RC model (Elmore delay) t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

21. EE141 Combinational Circuits 21 t p as a Function of Fan-In t pL H t p (psec) fan-in Gates with a fan-in greater than 4 should be avoided. t pH L quadratic linear tptp

22. EE141 Combinational Circuits 22 t p as a Function of Fan-Out t p NOR2 t p (psec) eff. fan-out All gates have the same drive current. t p NAND2 t p INV Slope is a function of “driving strength”

23. EE141 Combinational Circuits 23 t p as a Function of Fan-In and Fan-Out  Fan-in: quadratic due to increasing resistance and capacitance  Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO

24. EE141 Combinational Circuits 24 Fast Complex Gates: Design Technique 1  Transistor sizing  as long as fan-out capacitance dominates  Progressive sizing In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks

25. EE141 Combinational Circuits 25 Fast Complex Gates: Design Technique 2  Transistor ordering C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL critical path charged 1 0101 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L 1 1 0101 charged discharged

26. EE141 Combinational Circuits 26 Fast Complex Gates: Design Technique 3  Alternative logic structures F = ABCDEFGH

27. EE141 Combinational Circuits 27 Fast Complex Gates: Design Technique 4  Isolating fan-in from fan-out using buffer insertion CLCL CLCL

28. EE141 Combinational Circuits 28 Fast Complex Gates: Design Technique 5  Reducing the voltage swing  linear reduction in delay  also reduces power consumption  But the following gate is much slower!  Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) t pHL = 0.69 (3/4 (C L V DD )/ I DSATn ) = 0.69 (3/4 (C L V swing )/ I DSATn )

29. EE141 Combinational Circuits 29 Sizing Logic Paths for Speed  Frequently, input capacitance of a logic path is constrained  Logic also has to drive some capacitance  Example: ALU load in an Intel’s microprocessor is 0.5pF  How do we size the ALU datapath to achieve maximum speed?  We have already solved this for the inverter chain – can we generalize it for any type of logic?

30. EE141 Combinational Circuits 30 Buffer Example For given N: C i+1 /C i = C i /C i-1 To find N: C i+1 /C i ~ 4 How to generalize this to any logic path? CLCL InOut 12N (in units of  inv )

31. EE141 Combinational Circuits 31 Logical Effort p – intrinsic delay (3kR unit C unit  ) - gate parameter  f(W) g – logical effort (kR unit C unit ) – gate parameter  f(W) f – effective fanout Normalize everything to an inverter: g inv =1, p inv = 1 Divide everything by  inv (everything is measured in unit delays  inv ) Assume  = 1.

32. EE141 Combinational Circuits 32 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

33. EE141 Combinational Circuits 33 Logical Effort  Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates  Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current  Logical effort increases with the gate complexity

34. EE141 Combinational Circuits 34 Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3

35. EE141 Combinational Circuits 35 Logical Effort of Gates Fan-out (h) Normalized delay (d) t 1234567 pINV t pNAND F(Fan-in) g = p = d = g = p = d =

36. EE141 Combinational Circuits 36 Logical Effort of Gates Fan-out (h) Normalized delay (d) t 1234567 pINV t pNAND F(Fan-in) g = 1 p = 1 d = h+1 g = 4/3 p = 2 d = (4/3)h+2

37. EE141 Combinational Circuits 37 Logical Effort of Gates

38. EE141 Combinational Circuits 38 Add Branching Effort Branching effort:

39. EE141 Combinational Circuits 39 Multistage Networks Stage effort: h i = g i f i Path electrical effort: F = C out /C in Path logical effort: G = g 1 g 2 …g N Branching effort: B = b 1 b 2 …b N Path effort: H = GFB Path delay D =  d i =  p i +  h i

40. EE141 Combinational Circuits 40 Optimum Effort per Stage When each stage bears the same effort: Minimum path delay Effective fanout of each stage: Stage efforts: g 1 f 1 = g 2 f 2 = … = g N f N

41. EE141 Combinational Circuits 41 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

42. EE141 Combinational Circuits 42 Logical Effort From Sutherland, Sproull

43. EE141 Combinational Circuits 43 Example: Optimize Path Effective fanout, F = G = H = h = a = b = g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c

44. EE141 Combinational Circuits 44 Example: Optimize Path g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c Effective fanout, F = 5 G = 25/9 H = 125/9 = 13.9 h = 1.93 a = 1.93 b = ha/g 2 = 2.23 c = hb/g 3 = 5g 4 /f = 2.59

45. EE141 Combinational Circuits 45 Example: Optimize Path Effective fanout, H = 5 G = 25/9 F = 125/9 = 13.9 f = 1.93 a = 1.93 b = fa/g 2 = 2.23 c = fb/g 3 = 5g 4 /f = 2.59 g 1 = 1g 2 = 5/3 g 3 = 5/3 g 4 = 1

46. EE141 Combinational Circuits 46 Example – 8-input AND

47. EE141 Combinational Circuits 47 Method of Logical Effort  Compute the path effort: F = GBH  Find the best number of stages N ~ log 4 F  Compute the stage effort f = F 1/N  Sketch the path with this number of stages  Work either from either end, find sizes: C in = C out *g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

48. EE141 Combinational Circuits 48 Summary Sutherland, Sproull Harris

49. EE141 Combinational Circuits 49 Pass-Transistor Logic

50. EE141 Combinational Circuits 50 Pass-Transistor Logic

51. EE141 Combinational Circuits 51 Example: AND Gate

52. EE141 Combinational Circuits 52 NMOS-Only Logic 00.511.52 0.0 1.0 2.0 3.0 Time [ns] V o l t a g e [V] x Out In

53. EE141 Combinational Circuits 53 NMOS-only Switch A =2.5 V B C =2.5 V C L A =2.5 V C =2.5 V B M 2 M 1 M n Threshold voltage loss causes static power consumption V B does not pull up to 2.5V, but 2.5V - V TN NMOS has higher threshold than PMOS (body effect)

54. EE141 Combinational Circuits 54 NMOS Only Logic: Level Restoring Transistor M 2 M 1 M n M r Out A B V DD V Level Restorer X Advantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem

55. EE141 Combinational Circuits 55 Restorer Sizing 0100200300400500 0.0 1.0 2.0 W/L r =1.0/0.25 W/L r =1.25/0.25 W/L r =1.50/0.25 W/L r =1.75/0.25 V o l t a g e [V] Time [ps] 3.0 Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack

56. EE141 Combinational Circuits 56 Solution 2: Single Transistor Pass Gate with V T =0 Out V DD V 2.5V V DD 0V0V 2.5V 0V0V WATCH OUT FOR LEAKAGE CURRENTS

57. EE141 Combinational Circuits 57 Complementary Pass Transistor Logic

58. EE141 Combinational Circuits 58 Solution 3: Transmission Gate A B C C A B C C B C L C = 0 V A =2.5 V C =2.5 V

59. EE141 Combinational Circuits 59 Resistance of Transmission Gate

60. EE141 Combinational Circuits 60 Pass-Transistor Based Multiplexer GND V DD In 1 In 2 SS S S

61. EE141 Combinational Circuits 61 Transmission Gate XOR A B F B A B B M1 M2 M3/M4

62. EE141 Combinational Circuits 62 Delay in Transmission Gate Networks C R eq R CC R C In m (c)

63. EE141 Combinational Circuits 63 Delay Optimization

64. EE141 Combinational Circuits 64 Transmission Gate Full Adder Similar delays for sum and carry

65. EE141 Combinational Circuits 65 Dynamic Logic

66. EE141 Combinational Circuits 66 Dynamic CMOS  In static circuits at every point in time (except when switching), the output is connected to either GND or V DD via a low resistance path.  Fan-in of n requires 2n (n N-type + n P-type) devices  Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.  Requires on n + 2 (n+1 N-type + 1 P-type) transistors

67. EE141 Combinational Circuits 67 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

68. EE141 Combinational Circuits 68 Dynamic Gate In 1 In 2 PDN In 3 MeMe MpMp Clk Out CLCL Clk A B C MpMp MeMe Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 on ((AB)+C)

69. EE141 Combinational Circuits 69 Conditions on Output  Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.  Inputs to the gate can make at most one transition during evaluation.  Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

70. EE141 Combinational Circuits 70 Properties of Dynamic Gates  Logic function is implemented by the PDN only  number of transistors is N + 2 (versus 2N for static complementary CMOS)  Full swing outputs (V OL = GND and V OH = V DD )  Non-ratioed - sizing of the devices does not affect the logic levels  Faster switching speeds  reduced load capacitance due to lower input capacitance (C in )  reduced load capacitance due to smaller output loading (Cout)  no I sc, so all the current provided by PDN goes into discharging C L

71. EE141 Combinational Circuits 71 Properties of Dynamic Gates  Overall power dissipation usually higher than static CMOS  no static current path ever exists between V DD and GND (including P sc )  no glitching  Higher transition probabilities  Extra load on Clk  PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn  Low noise margin (NM L )  Needs a precharge/evaluate clock

72. EE141 Combinational Circuits 72 Issues in Dynamic Design 1: Charge Leakage CLCL Clk Out A MpMp MeMe Leakage sources CLK V Out Precharge Evaluate Dominant component is subthreshold current

73. EE141 Combinational Circuits 73 Solution to Charge Leakage CLCL Clk MeMe MpMp A B Out M kp Same approach as level restorer for pass-transistor logic Keeper

74. EE141 Combinational Circuits 74 Issues in Dynamic Design 2: Charge Sharing CLCL Clk CACA CBCB B=0 A Out MpMp MeMe Charge stored originally on C L is redistributed (shared) over C L and C A leading to reduced robustness

75. EE141 Combinational Circuits 75 Charge Sharing Example C L =50fF Clk AA B B B!B!B CC Out C a =15fFC c =15fFC b =15fFC d =10fF

76. EE141 Combinational Circuits 76 Charge Sharing B  0 Clk X C L C a C b A Out M p M a V DD M b Clk M e

77. EE141 Combinational Circuits 77 Solution to Charge Redistribution Clk MeMe MpMp A B Out M kp Clk Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

78. EE141 Combinational Circuits 78 Issues in Dynamic Design 3: Backgate Coupling C L1 Clk B=0 A=0 Out1 MpMp MeMe Out2 C L2 In Dynamic NANDStatic NAND =1 =0

79. EE141 Combinational Circuits 79 Backgate Coupling Effect Voltage Time, ns Clk In Out1 Out2

80. EE141 Combinational Circuits 80 Issues in Dynamic Design 4: Clock Feedthrough CLCL Clk B A Out MpMp MeMe  Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance.  The voltage of Out can rise above V DD.  The fast rising (and falling edges) of the clock couple to Out.

81. EE141 Combinational Circuits 81 Clock Feedthrough Clk In 1 In 2 In 3 In 4 Out In & Clk Out Time, ns Voltage Clock feedthrough

82. EE141 Combinational Circuits 82 Other Effects  Capacitive coupling  Substrate coupling  Minority charge injection  Supply noise (ground bounce)

83. EE141 Combinational Circuits 83 Cascading Dynamic Gates Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 V t ClkIn Out1 Out2 VV V Tn Only 0  1 transitions allowed at inputs!

84. EE141 Combinational Circuits 84 Domino Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp 1  1 1  0 0  0 0  1

85. EE141 Combinational Circuits 85 Why Domino? Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j Like falling dominos!

86. EE141 Combinational Circuits 86 Properties of Domino Logic  Only non-inverting logic can be implemented  Very high speed  static inverter can be skewed, only L-H transition  Input capacitance reduced – smaller logical effort

87. EE141 Combinational Circuits 87 Designing with Domino Logic M p M e V DD PDN Clk In 1 2 3 Out1 Clk M p M e V DD PDN Clk In 4 Clk Out2 M r V DD Inputs = 0 during precharge Can be eliminated!

88. EE141 Combinational Circuits 88 Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage

89. EE141 Combinational Circuits 89 Differential (Dual Rail) Domino A B MeMe MpMp Clk Out = AB !A!A!B!B M kp Clk Out = AB M kp MpMp Solves the problem of non-inverting logic 1 0 on off

90. EE141 Combinational Circuits 90 np-CMOS In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

91. EE141 Combinational Circuits 91 NORA Logic In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 to other PDN’s to other PUN’s WARNING: Very Sensitive to Noise!