1. CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20

2. Lecture Outline Mon, Oct 5 CEC 220 Digital Circuit Design Timing Diagrams Multiplexers Tri-State Buffers Slide 2 of 20

3. Timing Diagrams Mon, Oct 5 CEC 220 Digital Circuit Design Problem:  Real signals do NOT change instantaneously  Real hardware (i.e., gates) do not respond immediately Resolution:  Look at the signals vs time  Timing diagrams!! Slide 3 of 20

4. Timing Diagrams Effect of Gate Delays Mon, Oct 5 CEC 220 Digital Circuit Design Consider the simple circuit:  Assume that all gates have a 10 ns delay The outputs may not be defined at the start!! 10 ns Slide 4 of 20

5. 0 50 100 150 Timing Diagrams Hazards in Combinational Logic Mon, Oct 5 CEC 220 Digital Circuit Design Glitches:  The inverter has a 10 ns delay  The AND gate has a 5 ns delay A B C 10 ns 5 ns Slide 5 of 20 What should C=?

6. Timing Diagrams Hazards in Combinational Logic Mon, Oct 5 CEC 220 Digital Circuit Design A Static 1-Hazard A Static 0-Hazard Dynamic Hazards Slide 6 of 20

7. Multiplexers A 2:1 Multiplexer Mon, Oct 5 CEC 220 Digital Circuit Design A Multiplexer (or data selector) uses a control input(s) to select one of multiple inputs.   Z =0=1 Slide 7 of 20

8. Multiplexers 4:1 and 8:1 Multiplexers Mon, Oct 5 CEC 220 Digital Circuit Design 2 n input data lines n select lines 4:1 MUX 01230123 I0I1I2I3I0I1I2I3 A B Z Data Inputs Control Inputs Slide 8 of 20

9. Multiplexers An Example Mon, Oct 5 CEC 220 Digital Circuit Design Problem:  Use an 8:1 MUX to implement the following truth table. ABCZ 0000 0010 0101 0111 1001 1010 1101 1110 Slide 9 of 20

10. Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Problem:  Real world gates have limited output current drive capability (fan-out) The OR gate may NOT be able to Drive all of the AND gates Solution: Use a buffer Slide 10 of 20

11. Tri-State Buffers Mon, Oct 5 CEC 220 Digital Circuit Design A Tri-State or Three-State buffer  Output can be low, high, or high impedance (High-Z) B=0 B=1 Slide 11 of 20 A - Input B - Control C - Output A - Input B - Control C - Output

12. Tri-State Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Four kinds of Tri-State State buffers  Output can be low (0), high (1), or high impedance (Z) Slide 12 of 20 Non-Inverting Inverting Inverted Control Inverted Control & Op Inverted Control & Op

13. Tri-State Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Can use tri-state buffers to build a MUX: When B is low select A, or When B is high select C Slide 13 of 20 How would I build a 4:1 MUX?

14. Tri-State Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Problem: IC’s have a limited number of pins  Can use a given pin for either input or output Slide 14 of 20

15. Examples Mon, Oct 5 CEC 220 Digital Circuit Design Realize a 4:1 MUX, using an 8:1 MUX. Slide 15 of 20

16. Examples Mon, Oct 5 CEC 220 Digital Circuit Design Make an 8:1 MUX, using four 2:1 & one 4:1 MUX Slide 16 of 20

17. Examples Mon, Oct 5 CEC 220 Digital Circuit Design Use an 8:1 MUX to implement the function ABCf 0001 0010 0101 0111 1000 1010 1100 1111 ABCf 000 001 010 011 100 101 110 111 Slide 17 of 20

18. Examples Mon, Oct 5 CEC 220 Digital Circuit Design Use an 4:1 MUX to implement the function ABCf 0001 0010 0101 0111 1000 1010 1100 1111 Slide 18 of 20

19. Examples Mon, Oct 5 CEC 220 Digital Circuit Design Use an 2:1 MUX to implement the function ABCf 0001 0010 0101 0111 1000 1010 1100 1111 A BC 01 0010 0100 1111 1010 Slide 19 of 20

20. Next Lecture Mon, Oct 5 CEC 220 Digital Circuit Design Decoders and Encoders Read-Only Memories (ROMs) Slide 20 of 20