1. CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Friday, February 14 CEC 220 Digital Circuit Design Slide 1 of 18

2. Lecture Outline Friday, February 14 CEC 220 Digital Circuit Design Timing Diagrams Multiplexers Tri-State Buffers Slide 2 of 18

3. Timing Diagrams Friday, February 14 CEC 220 Digital Circuit Design Problem:  Real signals do NOT change instantaneously  Real hardware (i.e. gates) do not respond immediately Resolution:  Look at the signals vs time  Timing diagrams!! Slide 3 of 18

4. Timing Diagrams Effect of Gate Delays Friday, February 14 CEC 220 Digital Circuit Design Consider the simple circuit:  Assume that all gates have a 10 ns delay The outputs may not be defined at the start!! Slide 4 of 18

5. 0 50 100 150 Timing Diagrams Hazards in Combinational Logic Friday, February 14 CEC 220 Digital Circuit Design Glitches:  The inverter has a 10 ns delay  The AND gate has a 5 ns delay A B C Slide 5 of 18

6. Timing Diagrams Hazards in Combinational Logic Friday, February 14 CEC 220 Digital Circuit Design Slide 6 of 18 A Static 1-Hazard A Static 0-Hazard Dynamic Hazards

7. Multiplexers A 2:1 Multiplexer Friday, February 14 CEC 220 Digital Circuit Design A Multiplexer (or data selector) uses a control input(s) to select one of multiple inputs.   Z Slide 7 of 18

8. Multiplexers 4:1 and 8:1 Multiplexers Friday, February 14 CEC 220 Digital Circuit Design 2 n input data lines n select lines Slide 8 of 18 4:1 MUX 01230123 I0I1I2I3I0I1I2I3 A B Z Data Inputs Control Inputs

9. Multiplexers An Example Friday, February 14 CEC 220 Digital Circuit Design Problem:  Use an 8:1 MUX to implement the following truth table. ABCZ 0000 0010 0101 0111 1001 1010 1101 1110 Slide 9 of 18

10. Buffers Friday, February 14 CEC 220 Digital Circuit Design Problem:  Real world gates have limited output current drive capability The OR gate may NOT be able to Drive all of the AND gates Solution: Use a buffer Slide 10 of 18

11. Tri-State Buffers Friday, February 14 CEC 220 Digital Circuit Design A Tri-State or Three-State buffer  Output can be low, high, or high impedance (High-Z) Slide 11 of 18

12. Tri-State Buffers Friday, February 14 CEC 220 Digital Circuit Design Four kinds of Tri-State State buffers  Output can be low (0), high (1), or high impedance (Z) Slide 12 of 18

13. Tri-State Buffers Friday, February 14 CEC 220 Digital Circuit Design Can use tri-state buffers to build a MUX: When B is low select A, or When B is high select C Slide 13 of 18

14. Tri-State Buffers Friday, February 14 CEC 220 Digital Circuit Design Problem: IC’s have a limited number of pins  Can use a given pin for either input or output Slide 14 of 18

15. Examples Friday, February 14 CEC 220 Digital Circuit Design Realize a 4:1 MUX, using an 8:1 MUX. Slide 15 of 18

16. Examples Friday, February 14 CEC 220 Digital Circuit Design Make an 8:1 MUX, using four 2:1 & one 4:1 MUX Slide 16 of 18

17. Examples Friday, February 14 CEC 220 Digital Circuit Design Use an 8:1 MUX to implement the function f = A’B’C’ + A’BC’ + A’BC + ABC. ABCf 000 001 010 011 100 101 110 111 Slide 17 of 18

18. Examples Friday, February 14 CEC 220 Digital Circuit Design Use an 4:1 MUX to implement the function f = A’B’C’ + A’BC’ + A’BC + ABC. ABCf 0001 0010 0101 0111 1000 1010 1100 1111 Slide 18 of 18

19. Next Lecture Friday, February 14 CEC 220 Digital Circuit Design Decoders and Encoders Read-Only Memories (ROMs) Slide 19 of 18