1. CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers
Wed, February 18
CEC 220 Digital Circuit Design

2. CEC 220 Digital Circuit Design
Lecture Outline
Timing Diagrams
Multiplexers
Tri-State Buffers
Wed, February 18
CEC 220 Digital Circuit Design

3. CEC 220 Digital Circuit Design
Timing Diagrams
Problem:
Real signals do NOT change instantaneously
Real hardware (i.e., gates) do not respond immediately
Resolution:
Look at the signals vs time
Timing diagrams!!
Wed, February 18
CEC 220 Digital Circuit Design

4. Timing Diagrams Effect of Gate Delays
Consider the simple circuit:
Assume that all gates have a 10 ns delay
10 ns
10 ns
The outputs may not be defined at the start!!
Wed, February 18
CEC 220 Digital Circuit Design

5. Timing Diagrams Hazards in Combinational Logic
Glitches:
The inverter has a 10 ns delay
The AND gate has a 5 ns delay
10 ns
5 ns A 50
100
150 B C
Ideally, 𝐶=𝐴 𝐴 =0. In the “real world” glitches occur!!
Wed, February 18
CEC 220 Digital Circuit Design

6. Timing Diagrams Hazards in Combinational Logic
A Static 1-Hazard
A Static 0-Hazard
Dynamic Hazards
Wed, February 18
CEC 220 Digital Circuit Design

7. Multiplexers A 2:1 Multiplexer
A Multiplexer (or data selector) uses a control input(s) to select one of multiple inputs. =0 =1  Z 𝐴 I0 I1 
Z = I0 if 𝐴 is true, or
I1 if 𝐴 is true
Z = 𝐴 I0 + 𝐴 I1
Wed, February 18
CEC 220 Digital Circuit Design

8. Multiplexers 4:1 and 8:1 Multiplexers
4:1 MUX 1 2 3 I0 I1 I2 I3
A B Z
Data Inputs
2n input data lines
Control Inputs
n select lines
Wed, February 18
CEC 220 Digital Circuit Design

9. Multiplexers An Example
Problem:
Use an 8:1 MUX to implement the following truth table. A B C Z 1
Wed, February 18
CEC 220 Digital Circuit Design

10. CEC 220 Digital Circuit Design
Buffers
Problem:
Real world gates have limited output current drive capability (fan-out)
The OR gate may NOT be able to
Drive all of the AND gates
Solution: Use a buffer
Wed, February 18
CEC 220 Digital Circuit Design

11. CEC 220 Digital Circuit Design
Tri-State Buffers
A Tri-State or Three-State buffer
Output can be low, high, or high impedance (High-Z)
B=0
B=1
Wed, February 18
CEC 220 Digital Circuit Design

12. CEC 220 Digital Circuit Design
Tri-State Buffers
Four kinds of Tri-State State buffers
Output can be low (0), high (1), or high impedance (Z)
Wed, February 18
CEC 220 Digital Circuit Design

13. CEC 220 Digital Circuit Design
Tri-State Buffers
Can use tri-state buffers to build a MUX:
When B is low select A, or
When B is high select C
Wed, February 18
CEC 220 Digital Circuit Design

14. CEC 220 Digital Circuit Design
Tri-State Buffers
Problem: IC’s have a limited number of pins
Can use a given pin for either input or output
Wed, February 18
CEC 220 Digital Circuit Design

15. CEC 220 Digital Circuit Design
Examples
Realize a 4:1 MUX, using an 8:1 MUX.
Wed, February 18
CEC 220 Digital Circuit Design

16. CEC 220 Digital Circuit Design
Examples
Make an 8:1 MUX, using four 2:1 & one 4:1 MUX
Wed, February 18
CEC 220 Digital Circuit Design

17. CEC 220 Digital Circuit Design
Examples
Use an 8:1 MUX to implement the function A B C f 1 A B C f 1
Wed, February 18
CEC 220 Digital Circuit Design

18. CEC 220 Digital Circuit Design
Examples
Use an 4:1 MUX to implement the function A B C f 1
Wed, February 18
CEC 220 Digital Circuit Design

19. CEC 220 Digital Circuit Design
Examples
Use an 2:1 MUX to implement the function A B C f 1
A BC 1 00 01 11 10
Wed, February 18
CEC 220 Digital Circuit Design

20. CEC 220 Digital Circuit Design
Next Lecture
Decoders and Encoders
Read-Only Memories (ROMs)
Wed, February 18
CEC 220 Digital Circuit Design