1. Combinational Circuits by Dr. Amin Danial Asham

2. References  Digital Design 5 th Edition, Morris Mano

4. 3.DESIGN PROCEDURE (continue) V.Decoders (continue) The input variables represent binary numbers and the outputs represent the eight digits of a number in the Octal number system. However, 3-to-8 decoder can be used to decode any three bits code to 8 outputs, one for each number of the code. The output whose value is 1 represents the minterm equivalent to the binary number currently applied to the inputs lines.

5. 3.DESIGN PROCEDURE (continue) V.Decoders (continue) 2-to-4 decoder implements in NAND. Only one output is low at any time which represents the minterm selected by the inputs A and B The input E is an enable signal. When E=1 no output is 0 and hence the decoder is disabled. The decoder is enabled when E=0, that means the decoder is active-low enable.

6. 3.DESIGN PROCEDURE (continue) V.Decoders (continue)  Decoders with enable inputs can be connected to build larger decoders.  For example two 3-to-8 decoders can be use to build a 4-to-16 decoders as follows:

7. Decimal value of the inputs xyz xyzSC 000000 100110 201010 301101 410010 510101 611001 711111

9. 3.DESIGN PROCEDURE (continue) V.Encoders (continue)  To solve the problem of more than one input is active at the same time, the inputs are given priorities and hence the output will represent the highest priority input.  This type of encoders are called Priority Encoder.  As an example is 4-inputs priority encoder with the following truth table:  For each active input the lower priority inputs are considered don’t care since the output is depending on the highest priority input only.  The output V is used to indicate that there is at least one input is active. If all the inputs are zeros V=0 and hence no valid output on x and y lines. For V=0 x and y are considered don’t care denoted by X’s.

10. 3.DESIGN PROCEDURE (continue) V.Encoders (continue) Using the maps to get the Boolean functions of the priority encoder outputs. X in a row is replaced first by 0 and then by 1. we obtain all 16 possible input combinations. For example, the fourth row in the table, with inputs XX10, represents the four minterms, 0010, 0110, 1010, and 1110

13. 1 0 0 0 1 1 1 1 0 0 0 0 0 0/10/1 0/10/1 0/10/1  A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary information to the output line.  The AND gates and inverters in the multiplexer resemble a decoder circuit, and indeed, they decode the selection input lines

14. 3.DESIGN PROCEDURE (continue) V.Multiplexers (continue)  As in decoders, multiplexers may have an enable input to control the operation of the unit. When the enable input is in the inactive state the outputs are disabled, and when it is in the active state, the circuit functions as a normal multiplexer.  Multiplexer circuits can be combined with common selection inputs to provide multiple-bit selection logic.  For example, a quadruple 2-to-1 - line multiplexer. The circuit has four multiplexers, each capable of selecting one of two input lines.

15. 4 to 1 Mux

17. 3.DESIGN PROCEDURE (continue) V.Multiplexers (continue)  Three (Tri)-State gates  A tri state gate has tree states; two of them are equivalent to logic 0 and logic 1 states as in a conventional gate.  The third state is high output impedance, in which: I.The gates behaves like an open circuit, which means the output appears like to be disconnected. II.The circuit has no logic significant. III.The circuit connected to the output of the three-state gate is not affected by the inputs to the gate.  Three-state gates may perform any conventional such as; AND or NAND. However, the one most commonly used is the buffer gate.  The Three state buffer symbol looks like the conventional buffer with third control input C  In case of C=0. the output Y is disabled and the gate goes into the high impedance state regardless of the normal input A.  In case of C=1, the output is enabled and equals the normal input A.

18. 3.DESIGN PROCEDURE (continue) V.Multiplexers (continue)  Multiplexers can be built simply using Tri-state buffers.  A 2-to-1 line multiplexer can be constructed using two tri-state buffers and an inverter. o In case of the selection is 0 the upper buffer is enabled and the lower one is dis abled and hence y=A. o In case of the selection is 1 the lower buffer is enabled and the upper one id disabled and hence y=B.  In the same manner, 4-to-1 line multiplexer can be built using a 2-to-4 decoder to enable and disable the tri-state buffers. 0 1 Y=A 1 1 0 Y=B

20. Thanks