1. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 On-Chip Interconnects in Sub-100nm Circuits Sang-Pil Sim Sunil Yu Shoba Krishnan Dusan M. Petranovic Cary Y. Yang Back

2. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Motivation Effective Loop Inductance High Frequency Effects Frequency-Dependent RLC Model Non-Orthogonal Wires Conclusion Outline

3. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Wire versus Gate Delay

4. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Increases wire delay and worsens signal integrity when As technology advances, more wires will show inductive behavior Accurate RLC model is imperative for optimal design of today’s ULSI systems On-Chip Inductance (I) Gate delay (t r ) < RC Wire delay (RC l 2 ) < 2* flight time (2 l )

5. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Finding return path is not straightforward Partial inductance methodology alleviate the problem with a hypothetical return path On-Chip Inductance (II) Self Inductance Mutual Inductance I

6. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Partial inductance methodology is not appropriate for large circuits or full chip For multi-GHz freq., return current through capacitive coupling should be considered Non-orthogonal wires are being utilized  Effective loop inductance model for general high-frequency non-orthogonal wires becomes necessary Motivation

7. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Power grid: designated ground line Random lines: capacitive coupling path High-Freq. Digital Interconnect

8. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 LF: Low resistance path MF: Low inductance path HF: Low inductance by capacitive coupling R eff and L eff versus Frequency RLL & C Return path is determined by

9. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Given by partial inductance and resistance Frequency-dependent Loop Inductance and Resistance

10. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 R eff & L eff show sufficient linearity for hierarchical model construction S=3  m & P=40  m Foundation - Linearity

11. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Slight under-estimation of L at LF is caused by super-linearity Line – model, Symbol – FastHenry P=40  m (10  m, 300  m) (20  m, 365  m) (5  m, 340  m) Comparison with Field-Solver

12. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Slight under-estimation of L LF does not change overall impedance characteristics of wire Analytic & hierarchical model construction is validated for power grid configuration Effect of Super-Linearity in L LF

13. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Full-wave simulation (0.1 to 100GHz) RLCG extraction from the resulting S-parameters Random lines are left floating High-Frequency Effect

14. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Full Wave (random lines) SGGGG 2323210 2 Effect of Random Signal Lines

15. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Q-TEM mode approximation using SWFs at HF Separate SWFs for parallel and crossing lines Inductance extraction from capacitance Correlation between L and C

16. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Freq. Low Medium High R eff L eff Extraction from power grid, using energy equivalence from C, empirically L eff (  ) R eff (  ) C Freq-Dependent RLC Model

17. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 SGGGG 2323210 2 Comparison with Field Solver

18. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Can be modeled by an equivalent orthogonal power grid Same SWF as orthogonal is observed S = 3, 5, 10, 15, 20, 25  m, and P=50  m Diagonal Wires

19. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Conclusion Analytic and hierarchical construction of loop inductance is verified for power grid configuration Random signal line effect is quantitatively investigated, leading to an empirical model The wide-band characteristics of on-chip wire are incorporated into RLC circuit valid up to 100GHz Non-orthogonal architecture can be included into the proposed model

20. S A N T A C L A R A U N I V E R S I T Y Center for Nanostructures September 25, 2003 Partners Cadence Design Systems - Dr. N. Arora Intel - Dr. C. Dai KAIST - Prof. K. Lee Publications Sang-Pil Sim, et al., “An effective loop inductance model for general non-orthogonal interconnect with random capacitive coupling,” Technical Digest of IEDM, pp. 315-318, Dec. 2002. Sang-Pil Sim, et al., “High-frequency on-chip inductance model,” IEEE Electron Device Letters, vol. 33, pp.740-742, Dec. 2002. Sang-Pil Sim, et al., “A Unified RLC Model for High-Speed On-Chip interconnects,” IEEE Trans. on Electron Devices, vol. 50, p.1501, Jun. 2003.