1. VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY , BHOPAL
DEPARTMENT OF ELECTRONICS & COMMUNICATIONS
VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA

2. Chips are mostly made of wires called interconnect.
Wires are as important as transistors
Speed
Power
Noise
Interconnects in integrated circuits distribute clocks and other signals and provides power and ground to various integrated circuits .

3. Interconnects can either be local or global .
Local Interconnects
Local interconnects are the first and lowest level of interconnects .they usually connect Gate , Source and Drain in MOS technology and Emitter , Base and collector in Bipolar technology.

4. In MOS technology , a local interconnect polycrystalline serves as a gate electrode .
Silicide gates and silicides source/drain regions and material like TiN can also acts as a local interconnects .
Local interconnects shows higher resistivity than global . They are small in size but can withstand higher process temperature because they are deposited earlier in process flow than global interconnects.

5. Global interconnects
Global interconnects generally made of Al are all the interconnect levels above the local interconnects.
They often cover large distances between different devices and different parts of a chip. There fore they are low resistance metals.

6. Cross sectional view of MOS showing interconnects , contacts, vias separated by diaelectric layers .

7. Global interconnects provides clock and signal distribution between the functional blocks deliver power /ground to all functions.
Global interconnects occupy top one or two layers and more than 4 mm long .
They can be as long as half of the perimeter of the entire chip.

8. Ohmic contacts connect an interconnects with active regions and devices in silicon substrate.
A high resistive diaelectric layer usually SiO2 separates the active region to global interconnect.
An electric contacts are made between the interconnect and active region in silicon through openings in the diaelectric layers.
Contacts can be made between local and global interconnects because they are separated by same diaelectric. Connection between two levels of global interconnects are called vias.

9. Interconnect scaling

11. Wire Geometry Pitch = w + s Aspect ratio: AR = t/w
Old processes had AR << 1
Modern processes have AR  2
Pack in many skinny wires

12. Wire Resistance Rs = sheet resistance (W/square)
Count number of squares
R = RS * (# of squares)

13. Sheet Resistance Typical sheet resistances in 180 nm process Layer
Sheet Resistance (W/)
Diffusion (silicided)
3-10
Diffusion (no silicide)
50-200
Polysilicon (silicided)
Polysilicon (no silicide)
50-400
Metal1
0.08
Metal2
0.05
Metal3
Metal4
0.03
Metal5
0.02
Metal6

14. Wire Capacitance Ctotal = Ctop + Cbot + 2Cadj
Wire has capacitance per unit length
To neighbors
To layers above and below
Ctotal = Ctop + Cbot + 2Cadj

15. Capacitance Trend Parallel plate equation: C = eA/d
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
Increasing distance (s, h) decreases capacitance
Dielectric constant
e = ke0
e0 = 8.85 x F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics
k  3 (or less) as dielectrics use air pockets

16. Major criteria for interconnect design
Delay
Cross talk Noise
electro migration

17. THE END