1. ADVANCED HIGH DENSITY INTERCONNECT MATERIALS AND TECHNIQUES DIVYA CHALLA

2. INTRODUCTION  INTERCONNECTS connect the electronic circuits on a chip for proper functionality of the IC.  Interconnects can be Local (connections within transistors) or Global (connections between transistors including power, ground) Fig 1 Schematic showing interconnections

3. INTRODUCTION  The interconnects are separated from each other by dielectric materials.  Vias connect these interconnects throughout the IC layers.  Interconnects not only determine the functionality but also packaging density, reliability, manufacturing cost.  So as the IC technology progresses, the importance of Interconnect technology also increases because for overall performance, improving transistors must be complemented by the interconnect improvement.  The improving trends in IC technology generate new constrains and requirements for global and local interconnects.

4. INTERCONNECT MATERIALS  To reduce the size of the IC, the interconnect widths are reduced and the connections get closer which increases the capacitance and resistance. Fig 2. Interconnect structure for RC analysis R = k L/WH (k=resistivity, L : length, W: Width, H: Height) C1 = K ox E o HL/L s (K ox : dielectric constant, E o permittivity of free space)

5. INTERCONNECT MATERIALS  This increase in R and C increases the RC delay of the circuit. But in order to reduce the Interconnect delay, RC delay must be low.  As C increases, crosstalk increases and also Power dissipation increases (P d =CV 2 F)  To decrease the Interconnect pitch we can add more layers, but adding more layers leads to higher manufacturing cost and yield losses.  To lessen these constrains, new materials must be used for the Interconnects and also the techniques of integration must be changed.

6. INTERCONNECT MATERIALS REQUIREMENTS  Low resistivity Interconnect materials.  Low dielectric constant (porous and mechanically weak).  Good adhesion.  Ability to withstand the chemicals and high temperatures required in the fabrication process.  Resistance to electromigration.  Ease of deposition of thin films of the material.  Ability to be defined into fine patterns.  Ability to be thermally oxidized.

7. EVOLUTION OF INTERCONNECT MATERIALS  Aluminum was first used as an Interconnect material but it was replaced with Cu in 1997 as it has better metallic conductivity and resistance to electromigration.  Introduction of Cu is not sufficient for todays rapid improvements. The interconnect performance by use of Cu is somehow limited.  They found Ag which shows an improvement of 7% but when compared to the increase in cost, it is not worthy.  Interconnect materials with improved material’s properties must still be explored to advance the improvement in the IC fabrication.  New Interconnects like Nano-Interconnects, Molecular Interconnects, Optical Interconnects are being explored.

8. INTERCONNECT TECHNOLOGIES  Along with interconnect materials, it is also essential that we have new interconnect techniques to form interconnects between multiple stacked layers.  In the level of integration, wafer scale technology is mostly used.  Although wafer interconnects require complex technologies, it limits the size and cost of the IC.  In wafer technology, all the layers are connected through vias.  For High density Interconnection (HDI), via hole size is reduced but we have to maintain manufacturability.

9. INTERCONNECTION THROUGH VIAS  Mechanical drilling is replaced by UV laser microprocessing (min diameter of 25um).  After formation of vias, electrical isolation is provided to the walls of the via by either Chemical Vapor Deposition, spray coating or lamination.  Metal tracks are formed on the front (top to bottom interconnect) and rear side (back side routing) of the via by depositing Cu layer by electrochemical deposition. Fig 3. Interconnection over whole via bottom

10. LEAD FREE SOLDER NANOCOMPOSITES  Shrink in size  decrease in spacing between solder interconnects.  Also, thermo-mechanical fatigue due to thermally induced stresses that arise due to mismatch between Coefficient of Thermal Expansion(CTE) of solder and components in the circuit.  So, the conventional solders are passed through Carbon Nanotubes where multi-walled carbon nanotubes are incorporated into lead free solder.

11. LEAD FREE SOLDER NANOCOMPOSITES  The melting point improved.  The wettability between solder and substrate improved.  This also showed reduced CTE values.  Improvement in strength of Nanocomposites  decrease in dislocation due to CTE mismatch.  Composite solders with nanotechnology can improve the solder material’s properties which benefits the electronics assembly and packaging.

12. ROOM TO LOW TEMPARATURE DIRECT METAL BONDING  Cu bonding is not easy as gold because Cu is highly reactive (CuO2) and requires ultra high vacuum conditions.  Commonly known that Higher temperatures aid strength enhancement but observed that beyond 80 o c till 140 o c doesn’t improve bond strength.  Studies showed that when Cu is coated with Nanostructured Organic Coatings (NSOCs), it passivate Cu against CuO2 formation and hence bonds can be formed at temperatures close to ambient temperatures.  Investigations are being made to evaluate the NSOCs thickness to increase the bonding strength.

13. NANOINTERCONNECTION MATERIAL AND TECHNIQUES  Thermal oxide layer is grown on the substrate and CNT bumps were developed, inserted into one another and connected at room temparatures. Fig 4. CNT insertion process

14. NANOINTERCONNECTION MATERIAL AND TECHNIQUES  CNTs are comparable to gold on their electrical performance.  Nanotubes have no degradation after a period of 350 hours.  But fundamental issues still exist with CNT interconnects.  Innovations in architectures of CNT assembly are needed to use them widely.

15. TO DO  Metal Buried Interconnection  Other Interconnect technologies.

16. REFERENCES  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=527080 7 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=527080 7  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=139656 6 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=139656 6  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=481194 4 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=481194 4  http://jss.ecsdl.org/site/focus_issues/advanced_interconnects.xhtml http://jss.ecsdl.org/site/focus_issues/advanced_interconnects.xhtml