1. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 4. Introducing 90nm technology

2. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm Towards nano-scale Mos devices Specific features conclusion Summary

3. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 1. Towards nano-scale ST, Motorola and philips at Crolles, France 90nm core process Specific features for each partner

4. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 8386899295980104 0.1 80286 80386 486 pentium pentium II 1.0 0.2 0.3 2.0 0.05 Year Pentium IV 0.03 Itanium 07 Micron Sub-micron Deep-sub micron Ultra Deep-sub micron Nano 1. Towards nano-scale

5. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 1. Towards nano-scale Already 90nm? 130nm to 90nm improvement in logic density power saving per gate reduction in gate delay

6. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm Shallow Trench Isolation Triple Well Dual Vt Triple Oxide Option Dual Poly Gate Cu Metalup to 9 Layers with Low-k Metal pitch 0.3µm (m1-6), 0.6µm (m7-8), 1.2µm (m9) Wire Bond / Flip Chip Same Process for Logic & Mixed Mode (for SOC Application) Various power supplies supported: 3.3V, 2.5V, 1.8V, 1.2V, 1V 1. Towards nano-scale General CMOS 90nm Specifications

7. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 1. Towards nano-scale UMC CMOS 90nm

8. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 1. Towards nano-scale 300mm wafers In a 300mm fab… UMC taiwan

9. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 2. Mos devices UMC CMOS 90nm Specifications (www.umc.com)www.umc.com

10. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 2. Devices © Fujitsu

11. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm SP_Lvt 2. Mos devices SP SP_Hvt IO_2.5 IO_2.3

12. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 2. Mos devices Low Vt High speed (Or SP) Low leakage (Or HVt) High voltage: for I/Os Double-gate: Ultra-low leakage (Or LL) Output pad Input pad Critical path Standard Core Low power EEPROM, Flash Ultra low power High voltage

13. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 3. Specific features Triple well Shallow Trench Isolation

14. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 3. Specific features Triple well Shallow Trench Isolation

15. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm Cmos Embedded memories Volatile eDRAMSRAM Non volatile ROMEEPROMFRAM 80% of a system-on-chip Bottleneck for bandwidth 4. Embedded Memory

16. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 4. Embedded Memory Embedded DRAM (e-dram)

17. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 4. Embedded Memory Embedded DRAM (ST style)

18. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm The next major evolution? Less capacitance Less distance between nMOS and pMOS Less leakage CMOS compatible >50% faster circuits Kink effect Fully or partially depleted? 5. Silicon-On-insulator

19. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm Towards 2000 pins 6. Packaging

20. Master in Microelectronics technology and Manufacturing Management E. Sicard - introducting 90nm 6. Conclusion The ultra-deep submicron technologies introduce new features Low leakage MOS targeted for low power Double-poly MOS for EPROM/Flash memories Triple well for isolation and leakage control Embedded memory are key components for System-on-chip SOI has many promising features, some design issues pending