1. FNAL PMG Feb 5, 2004 1 DØ RunIIb Trigger Upgrade WBS 1.2 Paul Padley, Rice University for the DØ Trigger Upgrade Group

2. FNAL PMG Feb 5, 2004 2 Run IIb Luminosity Projections ~1.6e32 ~2.8e32 Accelerator draft plan: Peak luminosities Peak Luminosity (x10 30 cm -2 sec -1 ) You are here Peak FY04 ~5e31

3. FNAL PMG Feb 5, 2004 3 Ingredients of the Trigger Upgrade  Level 1 u Calorimeter trigger upgrade s sharpens turn-on trigger thresholds s more topological cuts u Calorimeter track-match s fake EM rejection s tau trigger u L1 tracking trigger upgrade (CTT) s improved tracking rejection especially at higher occupancies s inputs to Calorimeter track-match  Level 2 u L2 Processor upgrades for more complex algorithms u Silicon Track Trigger expansion s More processing power s use trigger inputs from new silicon layer 0

4. FNAL PMG Feb 5, 2004 4 Trigger Upgrade Project Institutions Boston, Columbia, Stony Brook, FSUSTT upgrade Orsay, Virginia, MSULevel 2  U. of ArizonaCal-Track match MSU, Northeastern, FSU,LangstonOnline software & integration Notre Dame, Saclay, Kansas, Manchester, Brown, Northeastern Simulation & algorithms Boston U., FNALTrack trigger ColumbiaCalorimeter: TAB (Saclay), MSU, UICCalorimeter: ADF Institution(s)Sub-project

5. FNAL PMG Feb 5, 2004 5 Management structure WBS 1.2: Trigger Upgrade P. Padley (Rice), D. Wood (Northeastern) WBS 1.2.1: Level 1 Calorimeter M.Abolins(MSU), H.Evans(Columbia) WBS 1.2.2: Level 1 Cal-track match K. Johns (Arizona) WBS 1.2.3: Level 1 Tracking M. Narain (Boston) WBS 1.2.4: Level 2 Beta upgrade R. Hirosky (Virginia) WBS 1.2.5: Level 2 STT upgrade U. Heintz (Boston) WBS 1.2.6: Trigger Simulation M. Hildreth (ND), E. Barberis (NEU) WBS 1.2.7: AFE upgrade A. Bross

6. FNAL PMG Feb 5, 2004 6 WBS 1.2.1: L1Cal ADC+digital filtering Clustering Global sums & topological

7. FNAL PMG Feb 5, 2004 7 Integration Tests Testing Data Transfer  Oct. Integration Test u SCL to ADF/TAB u ADF to TAB u TAB to Cal-Track  Bench Tests u ADF to GAB mechanism

8. FNAL PMG Feb 5, 2004 8 ADF Prototype MSU is on board working with SACLAY on next prototype On track to finalize changes and proceed to build a new prototype for testing in the early summer ADF Digital  fine ADF Analog  some noise largely due to driving voltage on ADCs new analog “unit cell” to improve noise performance

9. FNAL PMG Feb 5, 2004 9 TAB Prototype Valuable Data from Integration  TAB almost ready for Prod u only data to L2/L3 to test u > 6 months ahead of sched !

10. FNAL PMG Feb 5, 2004 10 What’s next  proto. GABnext week  ver.2 ADFlayout  new integration test u BLS to ADF u TAB to L2/L3 u ADF to TAB: extended running

11. FNAL PMG Feb 5, 2004 11 WBS 1.2.2: L1 cal-track matching  MTCxx (Trigger Cards) u Was submitted for production  UFB (Flavor Board) u Prototypes in hand u See next Slide  MTCM (Crate Manger) u Logic changes finished u Awaiting final checks

12. FNAL PMG Feb 5, 2004 12 L1 Cal Track Match  UFB (Flavor Board) u Prototypes in hand u L1MU “05” algorithm implemented in Stratix EP1S20F780C7 u H   successfully implemented and tested Universal Flavor board (daughter) Run IIb prototype MTCxx (mother) Run IIa version

13. FNAL PMG Feb 5, 2004 13 L1CalTrack Status  Infrastructure u VME crates, processors, power supplies, cables in hand u L1CTT to L1CalTrack cables installed during current shutdown (not terminated) u Crates installed in Movable Counting House  Commissioning u Plan is to use spare L1MU cards in L1CalTrack crates to establish communication with Trigger Framework and L3 u Replace spares with L1CalTrack cards as available

14. FNAL PMG Feb 5, 2004 14 WBS 1.2.3: L1 CTT  Digital Front End Axial (DFEA) daughter cards get replaced with new layout with larger FPGA’s (Xilinx Virtex-II XC2V6000). s Allows CTT to use “singlets”  Implemented prototype firmware (Boston U) u Includes equation files from all 4 momentum bins s p T >10 GeV, 5<p T <10 GeV, 3<p T <5 GeV, 1.5<p T <3 GeV u DFEA logic is implemented in two FPGAs  Currently undergoing tests with prototype DFEA card

15. FNAL PMG Feb 5, 2004 15 CTT Workshop  There was a very productive workshop at BU in January u included physicists and engineers u experts from Run2a commissioning involved u detailed discussion of algorithms and FPGA resources u emphasis on u firming up final hardware specifications u building a system that is fast and easy to commission It was so cold in Boston that this lobster turned blue!

16. FNAL PMG Feb 5, 2004 16 Some highlights from meeting  Specific FPGA choice was made (an important step)  There were a number of design changes suggested to make the upgrade easier to commission and minimize the impact on physics. u There should be a detailed specification of these changes by the end of the month.

17. FNAL PMG Feb 5, 2004 17 WBS 1.2.4: L2  eta Upgrade 6U board Compact PCI 9U board 64 bit <2MHz VME FPGA ECL Drivers 128 bits ~20 MHz MBus 32 bits 66MHz (max) Local bus 64 bits 33 MHz PCI J1 J2 J3 J5 J4 PLX 9656 UII Drivers Clk(s)/ roms Run IIa Betas are installed and running smoothly in all level 2 crates Run IIb strategy: purchase additional, more powerful commercial processors as late as reasonably possible.

18. FNAL PMG Feb 5, 2004 18 WBS 1.2.5: Silicon Track Trigger for Run IIb Technical Progress:  VME Transition Modules procured  With the approval of Layer 0, the procurement process was restarted.  Presently 90% of components are purchased. u (since this upgrade is just building more of an existing board procurements are the main issue)

19. FNAL PMG Feb 5, 2004 19 1.2.6 Simulation  The simulation effort has been reorganized  E. Barberis has become L3 manger along with M. Hildreth.  Recent simulation work has focused on the CTT but now a renewed effort to look at other aspects of the trigger upgrade, using the most recent experience in operations, is underway.  Plan to have a preliminary trigger list by summer.

20. FNAL PMG Feb 5, 2004 20 1.2.7 AFE II  Work on the AFE II board layout has started.  The specifications for Tript been defined and discussed with Ray Yarema’s group.  Ray Yarema’s group has started work on the Tript  Paul Rubinov is looking into Tript packaging options  Analysis continues on the impact of high luminosity and radiation damage on the CFT capability and how this will effect physics.

21. FNAL PMG Feb 5, 2004 21 Summary  Trigger upgrade proceeding at full speed  Prototypes in hand: u L1cal: splitter, TAB, VME/SCL, ADF u Cal-track: UFB, MTCxx proto in fabrication u L1CTT: DFEA preproduction I being tested  Plan to install with minimal downtime