Presentation is loading. Please wait.

Presentation is loading. Please wait.

Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of.

Similar presentations


Presentation on theme: "Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of."— Presentation transcript:

1 Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of Bari May 5 – 7, 2004 R. Antonicelli ST Belgium, Network Division

2 2 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division  When we write down a VHDL code, we must ensure a good matching between the digital circuit and our model  Thus, we need to check every signal and monitor the source code step by step  With a simulator tool we can easily reach these goals What is simulation good to?

3 3 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division  Modelsim by Mentor Graphics* * * * *  Leapfrog by Cadence* * *  Saber by Cadence*  VSS by Synopsys* What simulators are often used?

4 4 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division We discuss now about Modelsim simulator tool Modelsim EE/SE

5 5 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Modelsim EE: Graphic interface Main window

6 6 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Wave window Modelsim EE: Graphic interface

7 7 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Wave window Modelsim EE: Graphic interface

8 8 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Structure window Modelsim EE: Graphic interface

9 9 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Signals window Modelsim EE: Graphic interface

10 10 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Signals window Modelsim EE: Graphic interface

11 11 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Variables window Modelsim EE: Graphic interface

12 12 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division List window Modelsim EE: Graphic interface

13 13 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Source window Modelsim EE: Graphic interface

14 14 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Create a new library Modelsim EE: Lessons

15 15 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Compile a model Modelsim EE: Lessons

16 16 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Load a design Modelsim EE: Lessons

17 17 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Running a design Modelsim EE: Lessons

18 18 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Running a design Modelsim EE: Lessons

19 19 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Running a design Modelsim EE: Lessons

20 20 R. AntonicelliMay 5-7, 2004STMicroelectronics Belgium, Network Division Managing a design Modelsim EE: Lessons


Download ppt "Seminar for the Class of Digital Systems Electronics Seminar for the Class of Digital Systems Electronics The VHDL simulation environment Polytechnic of."

Similar presentations


Ads by Google