1. DEPT OF MODERN PHYSICS, USTC Electronics System of MC 2002.6.5 IHEP, Beijing ___________________________________________ Muon Group, USTC, Hefei

2. DEPT OF MODERN PHYSICS, USTC CONTENTS Overview of structure Readout System of MC Test System of MC

3. DEPT OF MODERN PHYSICS, USTC Structure of MC Electronics system Turn back to contents of Talk 3 Patrs Two subsystems Readout system Test subsystem Data, collected by FEC, transmitted to VME readout module by optic transmission module, and then saved into subevent buffer in VME readout mudule, to wait DAQ processing

4. DEPT OF MODERN PHYSICS, USTC CONTENTS Overview of structure Readout System of MC Test System of MC

5. DEPT OF MODERN PHYSICS, USTC Structure of MC Electronics system FEC data chain

6. DEPT OF MODERN PHYSICS, USTC A Data Chain A data chain contains 16 FECs A FEC has a 16-shift register in daisy chain Connection between FECs is: output port of last shift register on a FEC is connected to input port of first shift register on next FEC FEC 00 FEC 15 sys clk DECL Opt Trans FEC 01 A FEC Structure

7. DEPT OF MODERN PHYSICS, USTC Double Noise Rejection DISCFIFO Shift Regester Shift Reg of Last ch Shift Reg of Next ch ch X trigger FEC Structure Hit position information is transformed into data by DISC Data of DISC are shaped and kept in 3.2  s in Double Noise Rejection circuit to wait trigger If trigger is coming data are stored in FIFO / if not data are renewed 16 shift registers are connected as a 16-shift daisy chain DISC Circuit

8. DEPT OF MODERN PHYSICS, USTC Discriminator circuit for positive signal Discriminator circuit for negative signal DISC circuit Turn back to FEC structure

9. DEPT OF MODERN PHYSICS, USTC Double Noise Rejection DISCFIFO Shift Regester Shift Reg of Last ch Shift Reg of Next ch ch X trigger DNR Notes FEC Structure Hit position information is transformed into data by DISC Data of DISC are shaped and kept in 3.2  s in Double Noise Rejection circuit to wait trigger If trigger is coming data are stored in FIFO / if not data are renewed 16 shift registers are connected as a 16-shift daisy chain

10. DEPT OF MODERN PHYSICS, USTC Some notes of double noise rejection circuit Ues monostable chip instead of FIFO to keep data in 3.2  s in order to save cost of Muon readout system Use noise rejection circuit to shape a pulse with 200 ns-width and 3.2  s-delay to keep input Data of DISC and to reject noise, but System deadtime is a little big (3.3  s) Use double noise rejection circuit to reject noise and to reduce its deadtime, which just is 200 ns, it can be negligible One shot (monostable?) comes from Aleph Noise Rejection comes from Babar Double Noise Rejection will be used in BESIII Using monostable

11. DEPT OF MODERN PHYSICS, USTC But now we get wrong data – 111 because monostable at strip X 1 is retriggered again at t 3, and monostable at strip X 2 is retriggered too at same time Strip X 3.2µs Strip X 1 Strip X 2 trigger t1t1 t2t2 t3t3 t4t4 noise datum Noise of using monostable We can use noise rejection circuit to avoid noise at strip X 2, because acceptance window is too wide Data, corresponding to trigger at t 4, is appeared at t 2. So the correct data is 010 in the order of strip X 1, X, X 2 We can use un-retriggerable monostable to avoid noise at strip X 1 Noise rejection circuit

12. DEPT OF MODERN PHYSICS, USTC Noise rejection circuit LS221 DinDout Waveform of Noise rejection circuit Strip X 200ns M1 3.3µs M2 3.1µs Dout Acceptance window Shaped a pulse with 200 ns-width and 3.2  s-delay Make 3.3  s deadtime to system using un-retriggering monostable chip 74LS 221 Noise rejection circuit -- 1 Next: principle of noise rejection

13. DEPT OF MODERN PHYSICS, USTC Principle of noise rejection Strip X 2 Strip X 1 Strip X 200ns M1 3.3µs M2 3.1µs Dout M1 3.3µs M2 3.1µs Dout 200ns M1 3.3µs M2 3.1µs Dout 200ns Trigger Acceptance window Acceptance window and shaped pulse is narrow -- 200 ns-width Reject noise of strip X 1 and strip X 2 Get correct data 010 Deadtime to system is 3.3  s Noise rejection circuit -- 2 Next: Double Noise Rejection

14. DEPT OF MODERN PHYSICS, USTC Double noise rejection – 01 (structure) Dout Din LS221 LS123 Bank 1 Bank 2 There are two banks of noise rejection circuit Bank 1 used an un-retriggering monostable chip Bank 2 used a retriggering monostable chip Reduce deadtime to 200 ns Next: Principle of Double Noise Rejection

15. DEPT OF MODERN PHYSICS, USTC Double noise rejection – 02 (Principle of DNR) Bank 1 can catch first pulse appearing during 3.2  s using un-retriggering monostable chip 74LS221 Bank 2 can catch last pulse during 3.2  s using retriggering monostable chip 74LS123 In fact more than 2 pulses can not be appeared during 3.2  s under data input rate 2 kHz (probability is 2x10 -5 ) Output pulse of “OR” gate is pulse of bank 1 or pulse of bank 2 Pulse of bank 1 will be saved into FIFO if trigger corresponding to it coming/pulse of bank 2 will be saved if trigger corresponding to it coming; or both of them disappear if trigger is not coming Deadtime contributed to system by this circuit can be negligible Use counter chips to realize this circuit to avoid tolerance of extending Capacity and Resistance of monostable chips In fact double rejection circuit is a pipeline device with two cells Turn back to FEC block diagram

16. DEPT OF MODERN PHYSICS, USTC Double Noise Rejection DISCFIFO Shift Regester Shift Reg of Last ch Shift Reg of Next ch ch X trigger Data of DISC are shaped and kept in 3.2  s in Double Noise Rejection circuit to wait trigger Data are stored in FIFO as trigger is coming / data are renewed if trigger as trigger is not coming 16 shift registers are connected as a 16-shift daisy chain Depth of FIFO estimation FEC Structure

17. DEPT OF MODERN PHYSICS, USTC Size and depth of FIFO Contribution of FIFO to system deadtime can be negligible during time of data transmitting under this condition Turn back to FEC block diagram 1 bit for saving 1 Datum of a channel after available trigger Set 6 banks (1 bit for a bank) in FIFO to avoid new event data lost if new trigger coming during time transmitting all the data from 256-shift daisy chain through fiber to chain event buffer in VME readout module data lost is only 2.36 event data under 4kHz trigger rate for 8 hours of the running time by setting 6 banks

18. DEPT OF MODERN PHYSICS, USTC Double Noise Rejection DISCFIFO Shift Regester Shift Reg of Last ch Shift Reg of Next ch ch X trigger Shift register Data of DISC are shaped and kept in 3.2  s in Double Noise Rejection circuit to wait trigger Data are stored in FIFO as trigger is coming / data are renewed if trigger as trigger is not coming 16 shift registers are connected as a 16-shift daisy chain FEC Structure

19. DEPT OF MODERN PHYSICS, USTC Shift register 256 data go out at a port of data chain in series with differential ECL standard Turn back to MC electronics system In a FEC 16 shift registers get data in parallel In a chain of data 16 FECs, connected in a daisy chain, contains 256 bits FEC15 FEC 00 Shift 15 Shift 00 Sysclk Chain data out DECL

20. DEPT OF MODERN PHYSICS, USTC Configure of MC Electronics system FEC in Detector Ex-Box off Detector VME Crate in Contr Room Extended box

21. DEPT OF MODERN PHYSICS, USTC NIM modules in extended box Opt trans 1 Opt trans 2 Opt trans 3 Test Func Gen Test sig distr 1 Test sig distr 2 Thr vol Gen Thr vol distr 1 Thr vol distr 2 Sysclk distr 1 Sysclk distr 2 Trig sig distr 1 Trig sig distr 2 Power Supp 1 Power Supp 2 Power Supp 3 Optic transmission Optic transmission modules A Test Function Generator module A Threshold voltage Generator module There are: Some distribution modules Some power supply modules

22. DEPT OF MODERN PHYSICS, USTC TTL DECL chain00 Multiplexer ( Encoder) Trans Drv Contrl DECL chain01 DECL chain15 Fiber Multiplexer (De coder) Contrl Trans Receiv Clk 20MHz TTL chain00 TTL chain01 TTL chain15 Optic transmission 4096 data in 16 chains, loaded into the encoding chip in parallel delivered to the receiver chip over a serial channel reconstructed into its original parallel codes in decoding chip Turn back to Elec. System

23. DEPT OF MODERN PHYSICS, USTC Configure of MC Electronics system FEC in Detector Ex-Box off Detector VME Crate in Contr Room VME Readout module

24. DEPT OF MODERN PHYSICS, USTC VME Readout Module Chain Event Buffer 6×4 × 4-byte Sub- event Buffer 24×64 × 4-byte Test Ch 00 Series to parallel Data SPPRS VMEBUSVMEBUS Ch 15 Ch 01 Test Switch ACQ For data acquisition: 1.Data suppressions 2.Data saved into chain event buffer 3.Data into subevent buffer Format of data suppression Two work mode For Test: 1.Series data to parallel 2.Data saved into chain event buffer 3.Data into subevent buffer

25. DEPT OF MODERN PHYSICS, USTC Format of data suppression 0 Suppress FEC Adds （ 10-bit ） FEC Adds （ 10-bit ） Undef （ 6-bit ） FEC data （ 16-bit ） Suppress by FEC CH.adds （ 4 -bit ） Undef （ 2-bit ） as long as a datum of one channel on a FEC appears, data of whole 16 channels on a FEC as a 16-bit word will be stored 10-bit code expresses the address of the 625 FECs 16-bit code expresses the data of 16 channels, each channel occupying one bit Number of compressed data for an event is 600 bytes if 100 hits/event Store datum 1 and suppress datum 0 10-bit code expresses address of the 625 FECs 4-bit code expresses address of channels of a FEC Number of compressed data for an event is 1000 bytes if 100 hits/event Depth estimation of chain event buffer Use method of Suppressing by FEC in our design

26. DEPT OF MODERN PHYSICS, USTC Chain Event Buffer 6×4 × 4-byte Sub- event Buffer 24×64 × 4-byte Test Ch 00 Series to parallel Data SPPRS VMEBUSVMEBUS Ch 15 Ch 01 Test Switch ACQ Depth estimation of chain event buffer Set more banks to avoid the event data lost if the trigger signal comes again during the time of the transmitting event data from chain event buffer into subevent buffer Will lose 1.97 event data under 4kHz trigger rate for 8 hours if 6 banks of the chain event buffer are set This event data lost can be negligible Depth estimation of subevent buffer

27. DEPT OF MODERN PHYSICS, USTC Chain Event Buffer 6×4 × 4-byte Sub- event Buffer 14×64 × 4-byte Test Ch 00 Series to parallel Data SPPRS VMEBUSVMEBUS Ch 15 Ch 01 Test Switch ACQ Depth estimation of subevent buffer Set more banks to avoid the event data lost if the trigger signal comes again during the time of the DAQ processing Will lose 1.24 event data under 4kHz trigger rate for 8 hours if 14 banks of the chain event buffer are set This event data lost can be negligible Turn back to contents of talk

28. DEPT OF MODERN PHYSICS, USTC CONTENTS Overview of structure Readout System of MC Test System of MC

29. DEPT OF MODERN PHYSICS, USTC Test subsystem Test cntr Func Gen Sig to FEC VME Test Control Module

30. DEPT OF MODERN PHYSICS, USTC VME test control module ==== commands of test subsystem ==== WRP – write pattern register to select pulse generation (yes/no) WRC – write control register to adjust pulse width, amplitude and polarity RDP – read pattern register to check command data RDC – read control register to check command data Turn back to Test Subsystem Opt output Command Buffer VME Bus interface Fiber

31. DEPT OF MODERN PHYSICS, USTC Test subsystem Test cntr Func Gen Sig to FEC NIM Function Generator/Driver Distribution Module

32. DEPT OF MODERN PHYSICS, USTC NIM Function Generator/Driver Distribution Module Command data input here to decide signal pattern and width, amplitude 48 Signals to match 40 data chains after driving Turn back to Test Subsystem

33. DEPT OF MODERN PHYSICS, USTC Test subsystem Test cntr Func Gen Sig to FEC Driver on FEC

34. DEPT OF MODERN PHYSICS, USTC Test signal on a data chain of 16 FECs DISC 00DISC 15 Sig Drv FEC 00 Sig Drv FEC 01 Sig Drv FEC 15 Test Sig for a chain Test whole 16 FECs in a data chain by one signal of one channel in Function Generator Signal, drove again in a FEC, goes to 16 DISCs to test, then connected to next FEC in way similar to daisy chain 48 output channels of Function Generator to match 40 data chains

35. DEPT OF MODERN PHYSICS, USTC Structure of MC Electronics system The End The End

36. DEPT OF MODERN PHYSICS, USTC Thanks a lot