1. Tightly coupled INS/GPS system using particle filter D0928- system architecture and math functions Midterm presentation Students: Royzman Danny Peleg Nati Supervisor: Fiksman Evgeni

2. General overview (status) Math functions Infrastructure

3. Math functions Required functions: Sine, Cosine, Exponential,Square Root Proposed implementation: Sine, Cosine, Exponential : Straight-Forward variable-width variable-pipeline CORDIC algorithm. Square Root: Slightly tweaked variable-width variable-pipeline CORDIC algorithm

4. Cordic Algorithm http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC General CORDIC capabilities

5. CORDIC Algorithm PROSCONS 1 High accuracy calculations Multiple iterations needed to achieve high accuracy. Roughly, one iteration for each bit of input. 2 Ability to implement trigonometric, hyperbolic, linear functions Default input convergence limited Trigonometric functions default input convergence limited to ± π/2. Hyperbolic functions default input convergence limited to ± 1.1 Pre and Post processing units needed in order to increase input convergence range and calculate indirect functions (e.g. SQRT) 3 Low complexity HW requirements No multipliers. Each stage contains 3 adders/substractors, 2 shifters, single NOT gate Look-up table of default values needed. Approx. size: (pipe width X input word width) 4 Easily configurable for different implementation needs Variable-width linear pipeline(High TP) Constant width closed loop implementation (lowest HW requirements) Linear combinational logic implementation (asynchronous core) 5 Low sensibility to numeric format changes (e.g. changing input/output words width).

6. Proposed HW implementation Variable-width variable-pipeline CORDIC algorithm. ▫ Sine, Cosine functions implemented in single unit. ▫ Exponential, Square Root functions implemented in single unit each. ▫ Each unit contains Pre Process unit and a pipe core. ▫ Trigonometric functions unit will contain Post Process unit. ▫ Pipe core contains datapath and control stages. ▫ Pipe core will be combined from variable (1,2,4..32) amount of single stages, separated by a register. ▫ Default values: (HW cost/accuracy trade off).  Pipe stages total amount : 32 units.  Input/output width :32 bit.

7. Proposed HW implementation Pre-Processing unit Pipe Core Post-Processing unit Default values LUT InputOutput(s) Overview

8. Proposed HW implementation Single stage Overview http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC

9. Proposed HW implementation Pipe Core Overview http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC Pipe stages registers

10. Proposed HW implementation Trigonometric functions Pre and Post Process Unit Expansion of default convergence will be based on trigonometric identities: Therefore: if x>π/2 If x< -π/2 The sign inversion will be propagated through the pipe via control registers

11. Proposed HW implementation Square root Pre Process Unit With CORDIC algorithm, Square Root is not a directly computable function, but can be directly computed, so we will use the following identity: CORDIC PIPE x

12. Proposed HW implementation Hyperbolic functions Pre Process Unit In order to increase default convergence values, more (negative) CORDIC single stages will be needed. Moreover, different LUT and normalization constants will be needed.more (negative) CORDIC single stages will be needed

13. Proposed HW implementation Hyperbolic functions Pre Process Unit The stages amount to convergence increase ratio is concluded in the following table (M-negative stages amount, is maximal converging input). X. Hu, R. Huber, S. Bass, “Expanding the Range of Convergence of the CORDIC Algorithm”, IEEE Transactions on Computers. Vol. 40, Nº 1, pp. 13-21, Jan.1991. Daniel R. Llamocca-Obregón,Carla P. Agurto-Ríos; A FIXED-POINT IMPLEMENTATION OF THE EXPANDED HYPERBOLIC CORDIC ALGORITHM http://www.iberchip.org/iberchip2006/ponencias/106.pdf

14. Proposed HW implementation Hyperbolic functions default input convergence limited to ± 1.1 ▫ Pre-processing unit is required in order to increase convergence.  ! Typical input values required. C simulation resultsC simulation results Single stages amount limited to 32. In order to increase stages amount, input/output word size increase needed. Pipe core size limited to 2’s power (1,2,4..32 single stages in each pipe stage. 32 single stages means fully combinatory core). Word size limited to 32b Fixed point format. ▫ For exponential unit, maximum output number limited to 2 32. ▫ For SQRT unit, maximum input number is limited to 2 32. Constraints & limitations

15. Proposed HW implementation General: ▫Pipe core:  Control bits:  resetn : asynchronous low-active reset. Setting this bit to 0 will trigger ‘0’ output at all pipe registers.  enable : setting this bit to 0 will freeze the pipe core registers disregarding clock rising edges.  clk : registers clock. The registers are implemented as positive edge triggered.  Generic definitions:  pipe size : the amount of single stages in each pipe stage. Varies from 1 to 32, powers of 2, default value is 32, tuned for maximum TP.  width : the default word width will be used in our implementation, 32b. ▫ I/O:  see next slides Interface

16. Proposed HW implementation Trigonometric functions ▫ Input ▫ Output I/O Interface 313029282726252423222120191817 151413121110 9876543210 sign whole fraction 313029282726252423222120191817 151413121110 9876543210 sign fraction

17. Proposed HW implementation Other functions ▫ TBD, after typical values will be known, or some arbitrary decision will be taken. Interface

18. Infrastructure Ramp Up - as required ▫ 2 exercises written by Gadi Tuchman & Evgeni Fiksman, covering initial SW & HW acquaintance.  FIFO interfaces, SW registers access.  Multiport, RAM interfaces. ▫ General project infrastructure, including meetings with several groups & solving different issues.

19. Gannt Chart-Schedule

20. Q&A

21. Backup

22. אלגוריתם CORDIC סיבוב וקטור – התמרה כללית :

23. אלגוריתם CORDIC

24. הצובר הזוויתי:

25. אלגוריתם CORDIC שני מצבי עבודה : Rotation by Volder.1– מצב סיבוב 2.Vectoring – מצב וקטורי

26. אלגוריתם CORDIC בסה"כ עבור מצב סיבוב :

27. אלגוריתם CORDIC

29. Regular single stagesAdditional single stages Proposed HW implementation Hyperbolic functions Pre Process Unit Mathematical actions required, compared to regular single stage X. Hu, R. Huber, S. Bass, “Expanding the Range of Convergence of the CORDIC Algorithm”, IEEE Transactions on Computers. Vol. 40, Nº 1, pp. 13-21, Jan.1991. Daniel R. Llamocca-Obregón,Carla P. Agurto-Ríos; A FIXED-POINT IMPLEMENTATION OF THE EXPANDED HYPERBOLIC CORDIC ALGORITHM http://www.iberchip.org/iberchip2006/ponencias/106.pdf Back

30. Proposed HW implementation Hyperbolic functions Pre Process Unit C simulation results, acquired by running D0228 (Neta & Moti) project code. Maximum Exponential input : 375.704604 Minimum Exponential input : 0.12665 Average Exponential input : 14.15504 Convergence zone expansion: Total values checked : >1000000 (One million) Back Values coveredNegative stages 1%0(default) 63%5 87%10