1. TDC in ACTEL FPGA Tom Sluijk Hans Verkooijen Albert Zwart Fabian Jansen

2. OT FE Overview Amplify analog signals from anode wires (ASDBLR) Digital conversion (ASDBLR) Drift Time measurement (OTIS) Data Serialization and on optical link (GOL)

3. OT FEE Data (Now) Bit31 … 039 … 3247 … 40 … 287 … 280 DataHeader Drift Time Channel 0 Drift Time Channel 1 … Drift Time Channel 31 In Single-Hit Mode (currently used): Hit Position Drift Time Encoding No Hit1 1 b 6 b 5 b 4 b 3 b 2 b 1 Hit in 1 st BX0 0 b 6 b 5 b 4 b 3 b 2 b 1 Hit in 2 nd BX0 1 b 6 b 5 b 4 b 3 b 2 b 1 Hit in 3 rd BX1 0 b 6 b 5 b 4 b 3 b 2 b 1 6 bits drift-time (25 ns / 64 TDC channels) 2 bits : 3=Invalid, 0=1 st -BX, 1=2 nd -BX, 2=3 rd -BX 32 channels 8 bits / ch 32 bits HDR At 1.1 MHz 288 × 1.1 × 10 6 b/s = 0.3168 Gb/s 1.2672 Gb/s (80% of 1.6 Gb/s) PER FEE PER OTIS

4. Bit31 … 038 … 3245 … 39 … 255 … 249 DataHeader Drift Time Channel 0 Drift Time Channel 1 … Drift Time Channel 31 Assuming Single-Hit Mode Raw Data: Hit Position Drift Time Encoding No Hit1 b 6 b 5 b 4 b 3 b 2 b 1 Hit0 b 6 b 5 b 4 b 3 b 2 b 1 6 bits drift-time (25 ns / 64 TDC channels) 1 bits : 1=Invalid, 0=Valid OT FEE Data (Future) 32 channels 7 bits / ch 32 bits HDR PER FEE PER OTIS At 40 MHz 256 × 40 × 10 6 b/s = 10.24 Gb/s 40.96 Gb/s (30.72 Gb/s if 4 bits drift-time)

5. Zero-Suppression Scheme BitBit 31 … 036 … 3241 … 3747 … 4252 … 4858 … 53 ………… DataData Header OTIS0 No of Hits OTIS0 Addr. 1 st Hit OTIS0 DriftTime 1 st Hit OTIS0 Addr. 2 nd Hit OTIS0 DriftTime 2 nd Hit OTIS0 … Header OTIS1 No of Hits OTIS1 … Assuming Zero-Suppressed Data: 32 bits OTIS Header 5 bits for hits counter (max no of hits = 32) 5 bits (0-31) OTIS channel address 6 bits drift-time (25 ns / 64 TDC channels) OTIS Sub-Block Data Size = 32 bits + 5 bits + Occupancy  32  11 bits Total OT FE Data Size = 4  (37 bits + Occupancy  32  11 bits) N.B. We assume that the data receiver can identify to which of the 4 OTIS the data belong, either because they are serialized in “fixed- OTIS-order” or because the OTIS header contains such ID info. Otherwise, we need to add 2 bits to each “OTIS-sub-block”.

6. FEE Output Bandwidth Total OT FE Data Size = 4  (37 bits + Occupancy  32  11 bits) 6-bits RAW Data Bandwidth around 60% Occupancy E.g. 25% Occupancy  20 Gb/s seems a reasonable cutoff for “truncation” 4-bits RAW Data Bandwidth around 52% Occupancy

7. Upgrade LHCb Upgrade of LHCb has no L0-Trigger. Need a TDC that can make a time stamp every Bx. Radiation environment. At least 32 channels. December 20, 2015Outer Tracker Upgrade6

8. TDC in Actel FPGA ACTEL ProASIC Plus type APA075TQ100  CLK distribution and phase shift  TTC broadcasts decoding  TSTPLS  I 2 C interface to internal registers built with triple-voting SEU counter We have experience with ACTEL FPGAs: already used in present OT FEE (A. Zwart, OT CTRLBox, 2 / C-Frame)

9. December 20, 2015Outer Tracker Upgrade8 TDC in Actel FPGA (cont’d) Design of TDC in ACTEL Proasic3E FPGA because of the radiation properties. Design based on the Muonlab TDC; 2 channel TDC in Xilinx FPGA resolution of 500 ps, see: http://www.nikhef.nl/~hansvk/muonlab/http://www.nikhef.nl/~hansvk/muonlab/ First approach; 3 PLLs used to generate phase shifted 320 MHz signals of 0º, 45º, 90º and 135º  bins of 780 ps. 8 ch TDC was simulated, this design was hard to fit. The Actel Starter Kit has only 2 PLLs, so this design can not be used for tests. Second approach; 1 PLL at 320 MHz used to generate 8 phase shifted 40 MHz signals  bins of 1570 ps A 4 ch TDC is designed.

10. December 20, 2015Outer Tracker Upgrade9 TDC (second approach) PLL 320MHz BxClock 1 TDC Channel Phase Shifter Hit Register Time Encoder Output register Hit 1 TDC Channel Phase Shifter Hit Register Time Encoder Output register Hit

11. December 20, 2015Outer Tracker Upgrade10 Timing Diagram

12. Chip layout This part is used for the 4 channels December 20, 2015Outer Tracker Upgrade11

13. Test Procedures The design is fitted in an A3PE1500 208 PQFP and programmed in the Actel Starter Kit. The first test to determine the DNL: The onboard 40 MHz xtal oscillator is used as Bx Clock. An asynchronous pulse generator of 10 MHz generates a Hit signal with a flat distribution. Second test is a delay scan to determine the linearity: Pulse generator of 40 MHz supplies the Bx Clock. This signal is also delayed with a switchable NIM delay with steps of 0.5 ns to get the Hit signal. December 20, 2015Outer Tracker Upgrade12

14. Test Setup December 20, 2015Outer Tracker Upgrade13

15. Hit Distribution December 20, 2015Outer Tracker Upgrade14 “flat” input timing distribution artifact of counting both rising and falling edges

16. TDC Spectrum December 20, 2015Outer Tracker Upgrade15 TDC Response to “flat” input timing distribution |MAX (+) DNL | + |MAX (-) DNL |  0.77

17. Linearity December 20, 2015Outer Tracker Upgrade16 … …

18. Multi-Channels December 20, 2015Outer Tracker Upgrade17 Also checked channel relations on event-by-event basis

19. Outlook December 20, 2015Outer Tracker Upgrade18  Complete present checks o linearity checks o long-term stability o channel-to-channel variations o …  4 bits or more ??  control and readout logic o zero-suppression  Perform radiation hardness tests o what’s our goal?? o Present LUMI or  25??