1. 1 مرتضي صاحب الزماني 1 Routing Architectures

2. 2 مرتضي صاحب الزماني 2 معيارها routablility. سرعت : تعداد سوييچها در مسير. فضا. منابع اتصالي کم  کاهش امکان پياده سازي مدار مورد نظر منابع اتصالي زياد  اتلاف مساحت و کاهش بخش هاي منطقي.

3. 3 مرتضي صاحب الزماني 3

4. 4 4 مدل کلي LC Connection Block Switch Block LC Connection Block Switch Block LC Connection Block Switch Block LC Connection Block Switch Block

5. 5 مرتضي صاحب الزماني 5 اصطلاحات LE channel SW Wire Segment: قطعه سيمي که به يک سوييچ برنامه پذير منتهي شده است. يک يا چند سوييچ مي تواند به يک wire segment وصل شده باشد.

6. 6 مرتضي صاحب الزماني 6 اصطلاحات LE channel SW Track ( شيار ): دنباله اي از يک يا چند wire segment در امتداد يک خط. Channel: گروهي از Track هاي موازي. Connection Box: اتصال از وروديها و خروجيهاي يک LC به wire segment هاي کانال. Switch Box: اتصال بين wire segment هاي افقي و عمودي. channel

7. 7 مرتضي صاحب الزماني 7 Intermediate wiring channels A wire runs for L logic blocks: LE L=2 L=4 switch L=1 switch

8. 8 مرتضي صاحب الزماني 8 ملاحظات rouing چند نوع wire segment (XC4000).

9. 9 مرتضي صاحب الزماني 9 ملاحظات rouing 11223344 MPGA 1 1 223 344 آنتي فيوز برنامه ريزي نشده ( اتصال افقي قطع است ) آنتي فيوز برنامه ريزي شده ( اتصال افقي وصل است ) آنتي فيوز برنامه ريزي شده ( همه ي اتصالها وصلند ) افقيها به هم و عموديها به هم وصلند ( مگرآنکه برنامه ريزي شود ) Fully Segmented Channel

10. 10 مرتضي صاحب الزماني 10 ملاحظات rouing 11223344 MPGA 1 1 223 344 آنتي فيوز برنامه ريزي نشده ( اتصال افقي قطع است ) آنتي فيوز برنامه ريزي شده ( اتصال افقي وصل است ) آنتي فيوز برنامه ريزي شده ( همه ي اتصالها وصلند ) افقيها به هم و عموديها به هم وصلند ( مگرآنکه برنامه ريزي شود ) Fully Segmented Channel

11. 11 مرتضي صاحب الزماني 11 Architecture of FPGA Logic elements Interconnects I/Os

12. 12 مرتضي صاحب الزماني 12 Styles of FPGA interconnect Local Intermediate Global: –clock –Set/reset

13. 13 I/O Blocks مرتضي صاحب الزماني 13

14. 14 IO Blocks Provide access to the outside world Contain: –Buffers –Input registers –Output registers –MUXs –… مرتضي صاحب الزماني 14

15. 15 مرتضي صاحب الزماني 15 Altera Cyclone IOE

16. 16 IO Blocks Today FPGAs support multiple standards –Standard: Electrical aspects (e.g. voltage levels) –Each bank can be configured to generate/accept signals of a particular standard  FPGA can also be used to interface between different standards مرتضي صاحب الزماني 16

17. 17 I/O Block: Termination Resistors Fast signal edges  signal bounces back when different impedance at I/O –Discontinuities in the signals –Must add external termination resistors at pins  Very hard with today small pitch size مرتضي صاحب الزماني 17

18. 18 I/O Block: Termination Resistors Today FPGAs have internal configurable resistors to accommodate different board environments and I/O standards –DCI: Digitally-Controlled Impedance Simple rule of thumb: –For any signals with rise/fall times of < 500 ps, use termination resistors مرتضي صاحب الزماني 18

19. 19 Gigabit Transceiver –Traditional communication of large amount of data b/w devices: Bus –Large bus width (e.g. 64): Needs lots of pins Needs lots of tracks to connect devices Very hard to route these tracks in complex boards –Needs same length and impedance Hard to manage signal integrity مرتضي صاحب الزماني 19

20. 20 Gigabit Transceiver Gigabit Transceiver: –In high-end FPGAs, gigabit transceiver blocks use one pair of differential signals for very fast communication –Each block may have a number of (e.g. 4) such transceivers. مرتضي صاحب الزماني 20

21. 21 مرتضي صاحب الزماني 21

22. 22 FPGA as Interface Between Devices Gigabit Xceiver blocks can be configured to support several standards: –PCI Express –InfiniBand –… مرتضي صاحب الزماني 22

23. 23 Gigabit Transceiver Serial interface Point-to-point –  Each Xceiver can only talk to a single Xceiver on another device –Unlike buses with some devices hanging off

24. 24 Gigabit Transceiver Differential Pair: –A pair of tracks carrying complementary logic levels –Advantage: Less susceptible to noise (both affected equally)

25. 25 Inside Xceiver Block (TX)

26. 26 Inside Xceiver Block (RX)

27. 27 8b/10b Encoder In high data rate, circuit board and its track absorbs a lot of high frequency content of signal –Attenuated –Phase-shifted

28. 28 8b/10b Encoder Not serious problem in this case

29. 29 Consecutive Bits Inter-symbol Interference (ISI): Pessimistic view: –Receiver sees all ‘1’s! In reality: Must avoid sending 5 consecutive identical bits (‘1’s or ‘0’s) 8b/10b block: 8b data is augmented to 10b to guarantee that.

30. 30 FIFO Buffer Store data temporarily when too many words are arrived too closely together

31. 31 Polarity Flipper Flips ‘0’ to ‘1’ and vice versa if the receiving device expects data in flipped form

32. 32 Configurable Options Pre-emphasis (@ TX): –High-speed data rates cause signal attenuation –Pre-emphasis: first ‘0’ in a string of ‘0’s (first ‘1’ in a string of ‘1’s) are boosted with a slightly higher voltage

33. 33 Pre-Emphasis The amount of pre-emphasis can be configured for different circuit board environment: –E.g. 10%, 20%, 25%, and 33%

34. 34 مرتضي صاحب الزماني 34

35. 35 Pre-Emphasis The amount of pre-emphasis depends on –Position of FPGA in relation to other components –High-speed standard being employed –Board characteristics Can be determined by simulation

36. 36 Equalization More loss for high-frequency signals than low-frequency signals Equalization (@RX): –Boosting higher frequency signals more than lower ones –Can configure the amount of equalization –Can do pre-emphasis or equalization or both for a signal

37. 37 Equalization مرتضي صاحب الزماني 37

38. 38 Pre-Emphasis & Equalization

39. 39 References Maxfield, Design Warrior’s Guide to FPGA, 2004. RocketIO™ Transceiver User Guide, Xilinx, Gigabit Transceiver-ug024.pdf Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers, Xilinx, 2012.