1. 1 April 2009 NA62 DAQ meeting1 LKr calorimeter readout project H.Boterenbrood, A.Ceccucci, B.Hallgren, M.Piccini, H. Wendler

2. 1 April 2009 NA62 DAQ meeting2 Contents History (P253/NA48) & General Introduction LKr Consolidation, Smart Link Module (SLM) Calorimeter Recorder (CARE) Clock, Trigger, Slow control (Infrastructure), Crates, (PCs, etc.)

3. 1 April 2009 NA62 DAQ meeting3 Liquid Krypton Calorimeter Prototype used in SPS Tests 1991-95 192 channels 13248 channels Nucl. Instrum. Methods Phys. Res., A 574, 3 (2007) 433-471 Energy is contained in a cluster of ~ 100 cells P253 proposal 1990

4. 1 April 2009 NA62 DAQ meeting4 1:st Readout Electronics of year 1990 Very large JFET from “BNL” B.Hallgren,G.Laverriere, "A modular 100 ns shaper and linear fanout", NA48 Note 91-9.

5. 1 April 2009 NA62 DAQ meeting5 Present LKr Electronics readout principles https://twiki.cern.ch/twiki/bin/view/P326/LKr_Calorimeter Noise (MeV) Preamplifier 7.2 Shaper 3.5 Transceiver 2.5 Sum of above 8.3 (ADC 8.7b noise 1.0) (Coherent noise 0.5) Total 8.3 Typical noise per channel Σ noise / cluster = √ (83 2 + 50 2) = 97 MeV Shower cluster with 100 cells gives (But e.g.1993 beam test >> 100 MeV!) Calorimeter Pipeline Digitizer =CPD All LKr electronics is in a Faraday Cage Coherent Noise < 10uV READOUT

6. 1 April 2009 NA62 DAQ meeting6 Preamplifier output Transceiver output After differentiation ADC input signal LKr Analog Signal Processing (details) Undershoot! Baseline sampling needed. 2.5 us

7. 1 April 2009 NA62 DAQ meeting7 The beam is not strictly time-bunched and therefore there is no synchronous time signal correlated to the occurrence of interactions. SPS not like LHC ADC samples are dependent on the phase between the clock and the signal. Digital filter is used to extract the time of arrival off-line (<100 ps).

8. 1 April 2009 NA62 DAQ meeting8 CPD Analog Subcard = CPDAS 1996 Contains two custom circuits designed by NA48: KRYPTON 1.2 um BiCMOS gain switching, trigger stage, ADC control. MIGA 1um CMOS gatearray to handle the SRAM (divided into 200 us circular and 8k linear buffer). A typical event consists of 8 time samples of 12 bits. No trigger but a readout command (time stamp) has to arrive before 200 us. In the present module the readout of 512 words is in series and takes ~52 µsec! Very stable performance and enough spares available for at least 10 more years. (2 channels one on each side of the PCB)

9. 1 April 2009 NA62 DAQ meeting9 CPD module CPDTR card Analog Trigger card CPDMAC card with FASTBUS interface (on rear) 32 x CPDAS card Analog Cards (Shaper, ADC, Memory)

10. 1 April 2009 NA62 DAQ meeting10 LKr Physics Performance (with E in GeV) Energy, Position and Time

11. 1 April 2009 NA62 DAQ meeting11 LKr Consolidation Status 2005 27 optical links broken with no spares available anymore!

12. 1 April 2009 NA62 DAQ meeting12 LKr Consolidation During 2005 it become obvious that the LKr readout was “falling apart” and becoming in operational due to failing optical links. A crash program was initiated for the 2006-07 runs with the direct financial help by the directors Engelen and Lettow and resulted in the Smart Link Module (SLM). One SLM module can read a complete FASTBUS crate via LVDS links. The SLM (one board) consists of a FPGA, 1 GB DDR2 memory and Gigabit Ethernet with direct connection to a (small) PC-farm. Successful tests of the SLM modules were made in the 2006-07 runs. In October 2008 all of the old NA48 LKr readout was replaced with 28 SLM modules and a LKr new computer system. TBD more PC software and integration with rest of the system.

13. 1 April 2009 NA62 DAQ meeting13 Smart Link Board

14. 1 April 2009 NA62 DAQ meeting14 Rear of racks with 28 SLMsReadout Computers

15. 1 April 2009 NA62 DAQ meeting15 The Calorimeter Recorder (CARE)

16. 1 April 2009 NA62 DAQ meeting16 Calorimeter Recorder (CARE) Proposal Complete recording of all the data during one SPS burst. No triggers, only software readout requests via the GbE. This data is stored in on-board 16 or 32 GB DDR2 memory depending of the length of the SPS burst. Reuse the existing ~7000 CPDAS cards and the Analog Trigger cards. Only redesign the FASTBUS motherboard and digital board. Old and new CPDs should work in parallel in the same crate. Same clock features as the CPD with (Start of Burst) and End of Burst.

17. 1 April 2009 NA62 DAQ meeting17 Based on the SLM design (4 per CARE) The readout is done with 4 x 1 GbE links = ~320 MB/s but can be stretched out over the full 16 or 32 sec of the burst as it is done with the SLM. The MIGA gatearray on the CPDAS card is read out directly at 120 MB/s (the SRAM is not used). Use 4 “SLMs” for the control and readout. The 32 CPDAS is connected to FPGAs via 32x1.2 GB/s LVDS links. CARE Proposal Design

18. 1 April 2009 NA62 DAQ meeting18 Calorimeter Recorder

19. 1 April 2009 NA62 DAQ meeting19 Top Bottom STATUS of the CARE project The design of the PCB of the motherboard and digital board has been going on since Jan 8 of 2009. The work is greatly simplified because the same person who made the CPD PCB 1996 is available. The start of the PCB Protype fabrication is planned for mid of May? Lattice is used instead of the ALTERA with direct support available from Sr. Engineer at Lattice in Munich. Lattice DDR2 IP block is the necessary features as block transfers. Of course the FPGA software is based on the SLM experience.

20. 1 April 2009 NA62 DAQ meeting20 Moved to the CAREMB 4 x GbE

21. 1 April 2009 NA62 DAQ meeting21 Clock, Trigger, Slow control

22. 1 April 2009 NA62 DAQ meeting22 Clock requirements (identical to NA48) The NA48 clock system was designed for 960 MHz 8b FADCs by the Vienna group. CPDAS requirement are < 2 ps (rms) jitter (10 Bit ADC @ 40 MHz) Distributed as 80 MHz to get 40 MHz with 50% duty cycle needed by the ADC. The LVDS Serilizers needs low jitter clock. But long term stability is also important because used as time reference!

23. 1 April 2009 NA62 DAQ meeting23 (Trigger) No trigger needed! The bidirectional feature of the standard GbE can be used. An event at time x after the start of the Burst Signal is always stored at the same location in the DDR2 memory. The event is kept in the memory until it is overwritten during the next burst (16 or 32 sec). The CARE has analog trigger output signals which are used for the NA62 trigger processing.

24. 1 April 2009 NA62 DAQ meeting24 Slow Control (DCS) The Embedded Local Monitor Board (ELMB) is used via the CAN field bus (ATLAS standard). The ELMB stores constants and loads the serial control of the CPDAS when a module is powered. Only new updates has to be done via CAN or GbE (e.g. after calibration). ELMB monitors the large number of voltages in the CARE module (due to special power supply distribution to limit the coherent noise). The loading of the FPGA uses the Lattice Golden copy technique. The configuration can be updated as with the SLM (read and write of the serial flash memory) with GbE.

25. 1 April 2009 NA62 DAQ meeting25 (Infrastructure), Crates, (PCs, etc.) FASTBUS crates are available with spares. The old (mid 80s) Fastbus supplies should be replace with modern types, but the new CARE module prototype power consumption must be known. An offer from ELCOTRON SA exists. But there is always the problem of coherent noise and the cooling, so a very careful approach is needed. Ideally there should be a plug-in compatible model with new electronics inside but using the same mechanics!

26. 1 April 2009 NA62 DAQ meeting26 New Power Supplies = VME compatible FASTBUS has 25 slots versus 21 for VME The CPDAS card is 4 mm too high to fit in 2U VME! Therefore 28 FASTBUS versus 38 VME crates! 2005 Prices! Offer 2008

27. 1 April 2009 NA62 DAQ meeting27 QUESTIONS and COMMENTS?