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2. 9/15 2 Figure 11.17 A 2 M+N -bit memory chip organized as an array of 2 M rows  2 N columns. Memory SRAM organization organized as an array of 2 M rows  2 N columns Each chip can be organized 1-bit, 4, 8 or 16-bit wide Eg 64M-bit would be 64M x 1 2 26 bit address Storage cells organized as a square array

3. 9/15 Figure 11.23 A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the “dummy cell” arrangement shown in Fig. 11.25. SRAM cell Built with CMOS transistors Used in Cache Sense Amps are used to detect “sense” bit lines that have small signal values 3

4. 9/15 4 Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3  m, W = 0.2 to 100  m, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm. NMOS transistor structure Source (S), Drain (D), Gate (G) L channel length, W width of transistor NMOS transistor cross-section

5. 9/15 5 Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate. NMOS transistor +ve Gate (G) voltage  n-channel NMOS Transistor N-Channel MOSFET Built on p-type substrate MOS devices are smaller than BJTs MOS devices consume less power than BJTs source drain gate

6. 9/15 6 Figure 4.4 i D – v DS characteristics of MOSFET in Fig. 4.3 when the voltage applied between drain and source, v DS, is kept small. The device operates as a linear resistor whose value is controlled by v GS. NMOS transistor i D – V DS +ve V GS > V t & small V DS ===> resistive device iDiD V DS

7. 9/15 7 Figure 4.3 NMOS transistor with v GS > V t and with a small v DS applied. The device acts as a resistance whose value is determined by v GS. Specifically, the channel conductance is proportional to v GS – V t’ and thus i D is proportional to ( v GS – V t ) v DS. Note that the depletion region is not shown (for simplicity). NMOS transistor +ve V GS > V t & small V DS ===> acts like resistor Channel induced

8. 9/15 8 Figure 4.5 Operation enhancement NMOS transistor as v DS is increased. The induced channel acquires tapered shape, its resistance increases as v DS increased. Here v GS is kept constant at a value > V t. NMOS transistor +ve V GS > V t & increase V DS ===> resistance increases

9. 9/15 9 Figure 4.6 The drain current i D versus the drain-to-source voltage v DS for an enhancement-type NMOS transistor operated with v GS > V t. NMOS transistor id – V DS characteristic +ve V GS …. increase V DS

10. 9/15 Threshold Voltage V t Value of V G for which channel is “inverted 10 Characteristics of V T Inverting substrate from p-type to n-type  inversion layer in channel Controlled by inversion in channel Adjusted by implantation of dopants into the channel Can be positive or negative Influenced by the body effect  threshold voltage V T (or V t )

11. 9/15 11 Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant. NMOS circuit symbols (c) Is most common

12. 9/15 12 Figure 4.11 (a) n-channel enhancement-type MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) i D – v DS characteristics for a device with k’ n (W/L) = 1.0 mA/V 2. NMOS transistor, 3 regions Circuit & I D – V DS characteristic For Different V GS Cutoff V GS < V t Triode V GS > V t, small V DS Saturation; large V DS, flat I D

13. 9/15 13 Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that v GS and v DS are negative and i D flows out of the drain terminal. P-channel MOSFET PMOS (c)most common symbol (c)Circuit, with V & I

14. 9/15 14 Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n- type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device. CMOS structure, today’s ICs both NMOS & PMOS transistors PMOS formed in an n-well

15. 9/15 Why CMOS 15 Advantages Virtually, no DC power consumed No DC path between power and ground – V DD to load OR load to G nd Excellent noise margins (VOL=0, VOH=VDD) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pMOS size larger to achieve electrical symmetry

16. 9/15 16 Figure 4.53 The CMOS inverter. Digital CMOS Inverter (4.10)

17. 9/15 17 Figure 1.29 The VTC is approximated by three straight line segments. Note the four parameters of the VTC (V OH, V OL, V IL, and V IH ) and their use in determining the noise margins (NM H and NM L ). Inverter Transfer Characteristic VTC = voltage transfer characteristic Ideal inverter Typical inverter V oh = output high; V ol = output low; V il = max input interpreted as “0”;V ih = min input interpreted as “1”; V oh V ol V il V ih Noise margins NM L NM H

18. 9/15 18 Figure 1.32 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied in Section 4.10. CMOS inverter implementation The most common inverter

19. 9/15 19 Figure 4.56 The voltage transfer characteristic of the CMOS inverter. CMOS Inverter – Xfer Curve

20. 9/15 Figure 10.19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter. Other Inverter Implementations All NMOS - Not very popular -- FYI (a) pseudo-NMOS logic inverter.(b) The enhancement-load NMOS inverter. © The depletion-load NMOS inverter. 20