1. D FLIP FLOP DESIGN AND CHARACTERIZATION -BY LAKSHMI SRAVANTHI KOUTHA

2. What is a Flip Flop? – “ Flip Flop is a circuit that change states depending on the control signal and it is also the basic storage element in sequential logic” – Wikipedia

3. D FLIP FLOP TRUTH TABLE CLOCKDQ next Rising edge00 11 Non-RisingXQ

4. D FF SCHEMATIC Source: Wikipedia

5. D FF SCHEMATIC

6. REQUIREMENTS:  5 TWO-INPUT NAND GATES  1 THREE-INPUT NAND GATE TOOL USED: CADENCE VIRTUOSO (GlobalFoundaries 180nm CMOS Technology)

7. 2-INPUT NAND GATE 3-INPUT NAND GATE

8. W/L PMOSNMOS W600nm400nm L180nm W/L RATIO:

9. D FF SYMBOL

10. FF TEST BENCH

11. SCHEMATIC OUTPUT

12. FF LAYOUT

13. 2-INPUT NAND GATE LAYOUT

14. 3-INPUT NAND GATE LAYOUT

15. PMOS TRANSISTOR LAYOUT NMOS TRANSISTOR LAYOUT

16. FF LAYOUT OUTPUT RESPONSE

17. Some definitions of parameters:  Power Dissipation: Power is rate of energy transfer. Power dissipation is a measure of the rate at which energy is lost.  Propagation Delay: Time required by the system to travel from the input of a gate to the output.  Rise Time: The time required for a pulse to rise from 10% to 90% of its steady value.  Fall Time: The time taken for the amplitude of a pulse to decrease from 90% to 10% of the maximum value.  Setup Time: The minimum time the data should be steady before the clock event.  Hold Time: Minimum time the data signal should be held steady after the clock event. ( All definitions used are from Wiki )

18. POWER DISSIPATION CALCULATION

19. CALCULATION OF OTHER PARAMETERS

20. SCHEMATIC LAYOUT COMPARISON OF SCHEMATIC AND LAYOUT

21. SCHEMATIC LAYOUT COMPARISON OF SCHEMATIC AND LAYOUT

22. SCHEMATIC LAYOUT COMPARISON OF SCHEMATIC AND LAYOUT

23. SCHEMATIC LAYOUT COMPARISON OF SCHEMATIC AND LAYOUT

24. Temp(°C)Power diss in µW Prop delay in ps Rise time in ps Fall time in ps Setup time in ps Hold time in ps -1003.1377140.329.155.1 -503.2181.750.436.355.1 -253.1887.255.139.755.1 03.229359.943.6755.1 273.3499.664.947.855.1 503.17105.168.651.455.1 753.26111.1372.655.855.1 1003.36117.676.86055.1 1503.5213184.6869.655.1 2003.66146.793.997955.1 2503.85168.2102.392.255.1 3004.25208.2115.24112.855.1 3505.07339.3157183.255.1 SCHEMATIC PARAMETERS

25. Temp(°C)Power diss in µW Prop delay in ps Rise time in ps Fall time in ps Setup time in ps Hold time in ps -2003.04137.6979.0676.454.997 -1003.51218.05149.86121.85 4.997 -503.67256.12184.3146.85 4.997 -253.65275.67200.44159.35 4.997 03.83295.44216.08173.25 4.997 253.994316.94231.35188.65 4.997 504.184335.45244.352025 4.997 1004.301376.66276.01240.25 4.997 1504.48420.74297.13266.75 4.997 2004.865472323.07306.65 4.997 2505.225541.99352.9357.95 4.997 3005.542671.11571.792730.85 4.997 LAYOUT PARAMETERS

26. ERROR DISPLAYED

27. CONT……(ERROR DISPLAYED)

30. CONCLUSION:  The schematic of the flip flop shows normal range for the parameters calculated, but has unstable results for very low and very high temperature. Temperature range is -25°C to 200°C.  The layout also exhibits the same similarity in the calculations but results in unstable outputs. Temperature range is 0°C to 150°C.

31. REFERENCES:  http://www.ohio.edu/people/starzykj/webcad/ee415/VLSI/design/sizing/trans_si ze.htm  http://ece451web.groups.et.byu.net/cadence-help/tutA2.html#calc  http://ece451web.groups.et.byu.net/cadence-help/cadTOmat.html  http://ece451web.groups.et.byu.net/cadence-help/index.html  Wikipedia.org  http://www.falstad.com/circuit/e-edgedff.html  http://www.ece.ucsb.edu/Faculty/Johnson/ECE152A/L6%20- %20Latches,%20the%20D%20Flip-Flop%20and%20Counter%20Design.pdf  http://www.ittc.ku.edu/~yangyi/5%20Delay.pdf

32. THANK YOU!!!