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Axilog: Language Support for Approximate Hardware Design DATE 2015 Georgia Institute of Technology Alternative Computing Technologies (ACT) Lab Georgia.

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Presentation on theme: "Axilog: Language Support for Approximate Hardware Design DATE 2015 Georgia Institute of Technology Alternative Computing Technologies (ACT) Lab Georgia."— Presentation transcript:

1 Axilog: Language Support for Approximate Hardware Design DATE 2015 Georgia Institute of Technology Alternative Computing Technologies (ACT) Lab Georgia Institute of Technology University of Minnesota UC San Diego Amir YazdanbakhshDivya MahajanBradley Thwaites Jongse ParkAnandhavel NagendrakumarSindhuja Sethuraman Kartik RamkrishnanNishanthi RavindranRudra Jariwala Abbas Rahimi Hadi EsmaeilzadehKia Bazargan

2 Approximate computing Embracing error Relax the abstraction of near-perfect accuracy in general-purpose computing/communication/storage Allow errors to happen during computation/communication/storage – Improve resource utilization efficiency Energy, bandwidth, capacity, … – Improve performance Build acceptable systems from intentionally-made unreliable software and hardware components Avoid overkill and worst-case design 2

3 Avoiding Worst-Case Design Approximate Computing 3 Generality Precision Reliability Determinism Efficiency Performance Cost Physical Device Circuit Architecutre Compiler Programming Language Application Microarchitecture

4 Goals Design the first HDL for 1)Approximate Hw Design 2)Approximate Hw Reuse 3)Approximate Synthesis Criteria Approximate HDL shall be 1)High-level 2)Automated 3)Backward compatible 4

5 Safety in Hardware 5 Controller Datapath Clock Precise Approximate Precise

6 Axilog Annotations 6 Design Annotations relax (relax_local) restrict (restrict_global) Reuse Annotations approximate bridgecritical

7 Design Annotations 7

8 Relaxing Accuracy Requirements 8 module ripple_carry_adder(a, b, c_in, c_out, s) … full_adder f0(a[0], b[0], c_in, w0, s[0]) full_adder f1(a[1], b[1], w0, c_out, s[1]) relax (s); …

9 Relaxing Accuracy Requirements 9 module ripple_carry_adder(a, b, c_in, c_out, s) … full_adder f0(a[0], b[0], c_in, w0, s[0]) full_adder f1(a[1], b[1], w0, c_out, s[1]) relax (s); …

10 Scoping Approximation (relax_local) 10 module full_adder (a, b, c_in, c_out, s) … relax_local (s); … full_adder f0 (…) full_adder f1(…) relax (s[0]); …

11 Scoping Approximation (relax_local) 11 module full_adder (a, b, c_in, c_out, s) … relax_local (s); … full_adder f0 (…) full_adder f1(…) relax (s[0]); …

12 Restricting Approximation 12

13 Restricting Approximation 13

14 Restricting Approximation 14

15 Restricting Approximation Globally 15 module full_adder(a, b, c_in, c_out, s); … approximate output s; relax (s); … endmodule … restrict_global(s[31:0]);

16 Restricting Approximation Globally 16 module full_adder(a, b, c_in, c_out, s); … approximate output s; relax (s); … endmodule … restrict_global(s[31:0]);

17 Reuse Annotations 17

18 Outputs Carrying Approximate Semantics 18

19 Critical Inputs 19 … critical input reset; critical input clock; … Next State Logic State Register reset clock Output Logic

20 Bridging Approximate Wires to Critical Inputs 20 … and a1(s, a0, a1); relax (s); bridge (s); multiplexer m0(s, a0, a1, out); …

21 Bridging Approximate Wires to Critical Inputs 21 … and a1(s, a0, a1); relax (s); bridge (s); multiplexer m0(s, a0, a1, out); …

22 Baseline Synthesis Flow Highest frequency with minimum power and area 22

23 Relaxability Inference Analysis Identify the wires which are driving unannotated wires or annotated with restrict within the module under analysis 23 Marks any wire that affects a globally restricted wire as precise Identify the relaxed outputs of the instantiated submodules Safe to approximate gates Circuit under analysis with Axilog annotations

24 Approximate Synthesis Flow 24 Axilog Code Axilog Compiler Safe to Approximate Gates

25 Measurements Tools for Synthesis and Energy Analysis Synopsys Design Compiler Synopsys Primetime Timing Simulation with SDF back annotations Cadence NC-Verilog Standard Cell Library TSMC 45-nm multi-Vt Slowest PVT corner (SS, 0.81V, 0C) for baseline results 25

26 FIR # lines: 113 Signal Processing # Annotations Design: 6 Reuse: 5 InverseK # lines: 22,407 Robotics # Annotations Design: 8 Reuse: 4 ForwardK # lines: 18,282 Robotics # Annotations Design: 5 Reuse: 4 K-means # lines: 10,985 Machine Learning # Annotations Design: 7 Reuse: 3 Brent-Kung # lines: 352 Arithmetic Computation # Annotations Design: 1 Reuse: 1 26 Benchmarks Arithmetic Computation, Signal Processing, Robotics, Machine Learning, Image Processing Kogge-Stone # lines: 353 Arithmetic Computation # Annotations Design: 1 Reuse: 1 Wallace Tree # lines: 13,928 Arithmetic Computation # Annotations Design: 5 Reuse: 3 Neural Network # lines: 21,053 Machine Learning # Annotations Design: 4 Reuse: 3 Sobel # lines: 143 Image Processing # Annotations Design: 6 Reuse: 3

27 Energy Reduction Error ≤ 10% Error ≤ 5% 27

28 Area Reduction Error ≤ 10% Error ≤ 5% 28

29 10% Quality loss is nearly indiscernible to the eye Yet provides 57% energy savings 0% Quality Loss 5% Quality Loss 10% Quality Loss Output Quality Degradation in Sobel 29

30 Energy Reduction for Different PVT Corners 30 (SS, 0.81V, 125°C) (SS, 0.81V, 0°C)

31 Axilog 54% Energy Savings 1.9× Area Reduction 2-12 Code Annotations 31 First HDL for Approximation Design Reuse Automation High-level Backward-compatibility http://www.act-lab.org/artifacts/axilog

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