1. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Prototype Design of the Front End Module (FEM) for the Silicon Pixel Vertex Tracker in the PHENIX Experiment Sanjee Abeytunge Department of Physics and Astronomy Stony Brook University Stony Brook, New York. September 7, 2004

2. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Topics of Discussion ALICE1LHCB readout chip and its format Data Simulator Drift Chamber FEM and the Interface board Test Setup Results Outlook Conclusions and Issues

3. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York ALICE1LHCB readout chip Each chip reads 32 x 256 pixels Registers “hit” pixels; each pixel is a bit. Readout 32 x 256 bits at 10 MHz 8 chips (½ ladder ) are controlled and read out by the Pilot MCM Upon trigger Pilot MCM initiates readout of 8 chips sequentially on a 32-bit bus GOL allows transmission of 16-bit data @ 40 MHz GOL transmits via G-Link

4. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York ALICE1LHCB Format – according to the document available 100 ns long frames Each frame – 2 control words, 2 data words (16- bit wide) When there is no data – Idle frames ( 2 control words, 2 no data words) Bit specification identifies the event #, chip, first_word, last_word, fast_or etc.

5. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York ALICE Data Transmission Principle

6. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Bit Configuration for Cycles & Frames cavdav In every frameOnly Event Word frame“hit” Word frame

7. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Synchronizing Pilot MCM to the Link Receiver Pilot MCM near the detector; Link receiver in the control room; needs synchronization Link receiver must identify the different cycles Two step process to synchronize: 1) Synch Pilot MCM to the Link Receiver 2) Synch Link receiver to the proper data block

8. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Synch Pilot MCM to the Link Receiver Pilot near the detector; Receiver near the control room Identify slots with two control bits available in the G-Link protocol These two bits provide following signals: cav – Active when a control word available Active during slot 0 dav – Active when a data word available Active during slot 1a and slot 1b

9. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Synch Link receiver to the proper data block Identify the first_word signal : Activate bit 28 & 29 during slot0-cycle0 Identify the last_word signal : Activate bit 26 & 27 during slot0-cycle0 fast_or signal: Activated if at least one pixel has been “hit”

10. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Data Simulator (DS) Use National Instrument’s NI- 5411 pattern generator modules Use two modules: –One to simulate the “hit” data –One to simulate the cav & dav signals Use LabVIEW to talk to the generators Provide clock and trigger from the interface board FEM-DS Use “stepped trigger” mode External Trigger External Clock Digital Data Out SHC50-68 cable

11. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Data Simulator and FEM-DS flow diagram 16 bits FEM-DS Board LabVIEW PXI 8175 Controller NI 5411 Pattern Gen 1 NI 5411 Pattern Gen 1 Clock / Trigger

12. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York 32-bit word 16 bits Our Input File in Frame format 3 Idle Frames In stepped trigger mode 1 st 8 16-bit words are repeated until another trigger is received E V E N T D AT A 1 CONTROLWORDCONTROLWORD D AT A 2 D AT A 3 D AT A 4 Event Word Frame First “hit” Word Frame Includes real data from the first two data words CONTROLWORDCONTROLWORD CONTROLWORDCONTROLWORD N O D AT A N O D AT A CONTROLWORDCONTROLWORD C O NT R OL W O R D N O D AT A N O D AT A CONTROLWORDCONTROLWORD CONTROLWORDCONTROLWORD N O D AT A N O D AT A CONTROLFIRSTWORDCONTROLFIRSTWORD CONTROLWORDCONTROLWORD E V E N T D AT A CONTROLWORDCONTROLWORD CONTROLWORDCONTROLWORD CONTROLWORDCONTROLWORD C O N T R O L LA S T W O R D D AT A 5 1 D AT A 5 1 2 Last Word Frame Includes real data from the last two data words CONTROLWORDCONTROLWORD 256 32-bit words

13. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Bits and Data Input File It’s a 16-bit word Use the bit specs used by ALICE1LHCB A bit ‘on’ is 1, and a bit ‘off’ is 0 Convert the binary number to decimal number Program it into the input file

14. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Input Data File and the Input cav/dav File Remember we use the 2 nd pattern generator for cav/dav – 16 bits available Only two bits are needed – one for cav and another for dav Use bit 1 (10) for dav and bit 2 (100)for cav This means, program 2 for dav and 4 for cav for every Data Word & Control Word

15. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Drift Chamber FEM and the Interface board Use DC FEM to connect to the PHENIX DAQ Use an interface board to translate data from the data simulator into a format the DC FEM expects

16. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Block Diagram of the DC FEM

17. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York FEM-DS Interface Board Purpose: –Separate Control Words and “hit” Data Words. –Buffer data coming in at 20 MHZ and send out at 40 MHz. Receives timing, control and reset signals from the FEM Transmits trigger and clock to the DS Receives input data ( “hit” Data and cav/dav) from the DS Transmits “hit” Data to the FEM

18. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York FEM-DS Board Futurebus Connectors JTAG Conector EE-Prom Power In +5V Power-On Reset Fuse +3.3V Vol Regulator Low Profile Connectors +2.5V Vol Regulator FPGA Jumper LVPECL to LVTTL converter FEM or GTM Clk & Trig Selector Limo Conectors 50  Line Driver Trigger Out BNC Connectors Clock Out BNC Connectors General I/O Connector

19. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Control Signals Signals to the FEM_DS: –40 MHz clock (from FEM). –Collect_Data signal (from FEM) tells the FEM-DS to tell the generator to initiate pattern generation. –Read_Data signal (from FEM) tells the FEM-DS to start sending the data. Signals from the FEM-DS: –Trigger (Collect_Data) (to DS) –40MHz clock (to DS)

20. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Test Setup Includes key components of the PHENIX readout system – FEM, DCM & GTM FEM-DS interface board Data simulator

21. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Clock/Trig,Readout Control,Mode-bits etc. Data_Trigger( Collect_Data) 40 MHzClock 16 bitDataWords2 bitsfor cav / dav Data Simulator (DS) 256 16-bit Data Frames +3 16-bit Idle Frames +1 16-bit Event Frame =1040 Words NI5411 Module 2520 16-bit cav Words +520 16-bit dav Words =1040 Words NI5411 Module 1 PC LabVIEW Interface PXI 8175Controller 16 bit Data Words + 2bits for first / last words 40 MHz Clock Read_Data Collect_Data FEM-DS Board 514 Data Words 1040cav/dav Words + 526 control Words header + 514 Data Words + trailer G-Link Receiver Initialization/Status GTM PC G-Link Tranmitter FEM G-Link Tranmitter G-Link Receiver ARCNet FIFO Data-flow FPGA LOGIC ANALYZER 514 word data stream cav, dav and fastor can be used for timing analysis of Data Words FEM

22. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Test Setup ENDAT / Clock Data_Trig / Clock Read Data Collect_Data / Clock Data cav/dav Data “hit” Data GTM Simulator Board DCM Simulator Board FEMFEM-DS Board Data Simulator Logic Analyzer

23. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Measurement for full readout cycle 30.06 µs Fill frames for synch CollectData Data at DCM Read_Data Time needed to read 514 words

24. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York First “hit” Data Words Data 4Data 3Data 2 Event Numbers and 1 st word indication Beam Clk Counter Data 1

25. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York End of the transmission Data 512 and Last word indication Data 511 and Last word indication Parity Word User Word all zeros Status User Word

26. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Outlook Bring chip test board and readout cards to SB Learn to operate the system Develop the FEM prototype

27. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Issues Optical Rx/Tx from/to detector needs clarification due to lack of documentation. Should be resolved when chip & readout system available. G-Link replacement must have higher bandwidth –2 chips: 2 x (2 x 256) = 1024 16-bit words –½ ladder: 2chips x 4 = 4096 16-bit words –@ 40 MHz approximate readout time 120 µs –Need to transfer at a higher rate to avoid bottle neck –Full ladder readout time ~ 240 µs –Approximately factor of 5 increase in transmission bandwidth ArcNet – PHENIX decision

28. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Conclusions 256 pairs of 16-bit data words were read out in ~ 30 µs Equivalent to reading out 256 32-bit data words from one ALICE1LHCB chip Next phase of the prototype design of the FEM would be to readout 8 ALICE1LHCB chips, or ½ ladder within the time restrictions set by PHENIX

29. Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Acknowledgements Many thanks to –Axel Drees –Chuck Pancake