1. Curtis A. Nelson 1 Technology Mapping of Timed Circuits Curtis A. Nelson University of Utah September 23, 2002

2. Curtis A. Nelson 2 Advisors  Academic: Dr. Chris Myers, University of Utah  Industry: Dr. Ken Stevens, Intel Corporation  Unofficial: Other graduate students

3. Curtis A. Nelson 3 The Big Picture  Research area: Computer Aided Design  Specialty: Timed Asynchronous Circuits  Specifically: Technology Mapping

4. Curtis A. Nelson 4 Overview  Synchronous circuits depend on a central clock.  Clock routing and skew are serious design challenges.  Asynchronous circuits alleviate clocking problems.  Asynchronous advantages can be reduced by overhead.  Timed circuits can potentially remove this overhead.

5. Curtis A. Nelson 5 What are Timed Circuits?  Timed circuits use explicit timing information.  Timing assumptions can reduce the state space.  Reduced state space may simplify synthesis.  Correct operation relies on two-sided timing constraints. Constraints enable performance. Timing violations can cause failure.

6. Curtis A. Nelson 6 What is Technology Mapping?  Process of choosing gates for circuit implementation.  Matches synthesized equations to library elements.  Considers cost factors: area, delay, power, etc.  Combines the steps of: Decomposition. Partitioning. Matching / Covering.

7. Curtis A. Nelson 7 Synchronous Design Flow

8. Curtis A. Nelson 8 Timed Design Flow

9. Curtis A. Nelson 9 Hazards and Glitches  Hazards are combinations of delays or timing specifications that may produce glitches.  Glitches are transient, but incorrect logic levels on circuit outputs that likely result in failure.

10. Curtis A. Nelson 10 Decomposition  Reduces the synthesized circuit into base functions. Typically Inverters, 2-NAND, Storage element  Newly created nodes may introduce hazards.  Challenge for timed circuits: Decompose without creating hazards OR Show that hazards do not produce glitches on outputs.

11. Curtis A. Nelson 11 Decomposition Example

12. Curtis A. Nelson 12 Timing Helps Detect Hazards

13. Curtis A. Nelson 13 How is Hazard Checking Done?  Decomposition creates new nodes that must be checked for hazards. Adds variables to the state graph. Added variables must be checked for consistency. Inconsistent variables  hazardous node. Hazardous nodes must be flagged for covering.

14. Curtis A. Nelson 14 Hazard Checking - Coloring

15. Curtis A. Nelson 15 Hazard Checking - Propagation

16. Curtis A. Nelson 16 Hazard Checking - Done

17. Curtis A. Nelson 17 Where Timing Helps

18. Curtis A. Nelson 18 Matching / Covering  Matches decomposed logic to library cells.  Results depend on decomposition structure.  Nodes determined to be hazardous must be encapsulated within library elements.

19. Curtis A. Nelson 19 Structural Library Representation  All elements represented using base functions.

20. Curtis A. Nelson 20 Matching / Covering Example

21. Curtis A. Nelson 21 Conclusions  Timed circuits must be synthesized and mapped.  Hazards must be detected and eliminated.  Result: Hazard-free net-list of library components.  Timed circuits are becoming a viable alternative to synchronous design.

22. Curtis A. Nelson 22 Contributions  Using explicit timing to eliminate hazards.  Library matching with the intent to remove hazards.  Provide a complete timed circuit design flow.  Increase awareness of timed circuit design. CAD Tools for Timed Circuit Design  Industry