1. Power Integrity Test and Verification CK Cheng UC San Diego ckcheng@ucsd.edu 1

2. Outline Motivation Prediction Metrics Measurement Remarks 2

3. Motivation: Huge Analog Circuits Package: – Voltage regulator – Distributed RLC model Silicon Chips: – Through Silicon Vias – Micro Bumps – Metal wires 3

4. Power Integrity: One Major Challenge in Near Future Power network is expensive – takes +30% resources – Power Supply, Board, Package, Pins, Through Silicon Vias, Micro Bumps, Wires – VRM, Decoupling Capacitors, Equivalent Series Resistance Power network design becomes more stringent – Technology scaling, V drops, P increases – Equivalent Impedance Z=V/I=V 2 /P (P=VI) – 3D ICs: Same footprint, larger load. Power Networks: Huge analog circuits with tighter design margins 4

5. Prediction: Accuracy? Circuit Model: Millions to Billions of objects – Wide range of frequency – Extraction of huge 3 D structure – Model order reduction Current Load Model: Many possible patterns – Many IPs with many modes of operations – Frequency ranges, wave slopes, peaks, average – Vectorless patterns Simulation: No tools can handle all the details – CPU, Memory capacity – Small time steps and many steps – Very coarse model or local view of tiny details Prediction: temporal and spatial relation of whole system 5

6. Measurement Metrics – Static voltage drops – Dynamic peak, average drops – Electronic migration – Leakage power – Signal delay On-Chip Sensors – Under sampling – Excitation generation 6

7. Remarks 3D ICs – Bare die testing – Integration Standard – Interface – Current patterns Procedure – Mode setting – Static and dynamic behaviors – Worst case coverage 7