1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 4 Martin Kittel

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Results Phase 3 Slansky Adder Pipeline Depth = 5 values for ASIC P leak 153.6679 nW frequency f244 MHz E avg 0.2499478 metric4.069E-13

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Improvements No changes in the Design Cadence Encounter Aspect Ratio 1:1 has highest frequency Different optimizations: Optimize for leakage – worse metric Optimize netlist – worse metric … - every time the metric got worse Core Utilization

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Core Utilization

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Final Result Mandatory values for ASIC Timing ( T min / f max )4.358 ns / 229.463 Mhz Power (P dyn / P leak )749.24 μW / 157.21 nW E_avg0.249948 N_cycles41376 t OP 180.317 μs Metric442.680 fJ Core size35145 μm² Core utilization90 %

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock The final Chip Slide 6

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Thank you for your attention!