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© 2004 Xilinx, Inc. All Rights Reserved Adding a Processor System to an FPGA Design.

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Presentation on theme: "© 2004 Xilinx, Inc. All Rights Reserved Adding a Processor System to an FPGA Design."— Presentation transcript:

1 © 2004 Xilinx, Inc. All Rights Reserved Adding a Processor System to an FPGA Design

2 Adding Processor System to an FPGA Design - 4 - 3 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Objectives After completing this module, you will be able to: Utilize the integration between ISE and XPS to enhance the design flow Utilize the Xflow in XPS Describe the steps involved in creating a submodule by using XPS and integrating the submodule into a bigger system by using ISE List some of the advantages of UltraController 

3 Adding Processor System to an FPGA Design - 4 - 4 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline ISE: Project Navigator Integration – Top Level – Submodule UltraController Case Study XPS: Xflow Integration

4 Adding Processor System to an FPGA Design - 4 - 5 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only EDK: ISE Processor IP MPD Files system.ucf system.bit MHS File system.mhs PlatGen ISE Hardware Data2MEM download.bit Compile Link Object Files Executable Libraries Source Code LibGen MSS File system.mss EDIF IP Netlists bram_init.bmm bram_init_bd.bmm ISEISE Source Code Synthesis

5 Adding Processor System to an FPGA Design - 4 - 6 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only ISE Project Navigator Integration XPS provides integration on two levels: – The processor system is the top-level design – The processor system is a submodule What XPS does – Creates the ISE Project Navigator Project File (NPL) – Adds the BMM file to the project – Adds the HDL file to the project Top-level wrapper Submodule wrapper – Sets macro search path to \implementation directory The peripheral files (NGC) created by PlatGen

6 Adding Processor System to an FPGA Design - 4 - 7 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only ISE Project Navigator Integration Benefits – Allows you to add additional logic to the FPGA design – Allows you to synthesize the design by utilizing ISE supported synthesis tools – Allows you to control the FPGA implementation flow by using ISE Timing and constraints entry Implementation tool flow control Point tool control – FPGA Editor tool – Constraints Editor tool – ChipScope  Pro tool

7 Adding Processor System to an FPGA Design - 4 - 8 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Project Options Hierarchy and Flow Tab Design Hierarchy – Toplevel – Sub-module Top Instance Must use ISE flow Synthesis Tool – ISE XST – None, if third party tools are to be used Implementation Tool Flow – XPS – ISE (ProjNav) Provide directory and file name in the NPL File box

8 Adding Processor System to an FPGA Design - 4 - 9 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline ISE: Project Navigator Integration – Top Level – Sub-module UltraController Case Study XPS: Xflow Integration

9 Adding Processor System to an FPGA Design - 4 - 10 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only ISE: Top Level The project is created with the part and synthesis tool selected in XPS The processor system netlist will be hierarchical The following files are added – system.vhd: instantiates the processor system created in XPS – bram_init.bmm: BMM file used by Data2MEM – User IP creates a VHDL library and adds the IP sources to that library

10 Adding Processor System to an FPGA Design - 4 - 11 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline ISE: Project Navigator Integration – Top Level – Submodule UltraController Case Study XPS: Xflow Integration

11 Adding Processor System to an FPGA Design - 4 - 12 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only ISE: Sub-module The project is created with the part and the synthesis tool selected in XPS The following files are added – system_stub.vhd: instantiates the processor system created in XPS – system_stub.bmm: BMM file used by Data2MEM

12 Adding Processor System to an FPGA Design - 4 - 13 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline ISE: Project Navigator Integration – Top Level – Submodule UltraController Case Study XPS: Xflow Integration

13 Adding Processor System to an FPGA Design - 4 - 14 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only UltraController UltraController  key features – Completely self-contained PowerPC  system No external FPGA pins required – 32 general-purpose inputs and outputs – Ultra low power— 0.9 mW / MHz Easy to use – Code in “C” — Multiple reference designs available – No CPU buses, no RTOS required – Integrates with standard ISE design flow – Full debug support 32 gpio_in sys_clk gpio_out sys_rst jtag_cntlr UltraController

14 Adding Processor System to an FPGA Design - 4 - 15 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Inside the UltraController General-purpose controller based on the PowerPC – Growing family of solutions – Uses 8 or 16 BRAMs + 49 logic cells 8-kB instruction, 8-kB data 16-kB instruction, 16-kB data – JTAG debug support UltraController ROM 8kB PowerPC 405 gpio_in gpio_out sys_clk sys_rst jtag_cntl I/O RAM 8kB

15 Adding Processor System to an FPGA Design - 4 - 16 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only UltraController Benefits UltraController  provides flexibility for the following – Complex user interfaces (GUI or LCD display) – Sophisticated data and math manipulations – System monitoring and statistics gathering – Complex algorithms Maximizes logic efficiency by using the PowerPC  processor, because logic frees fabric for more functionality, performance, and intelligence Reduces cost by downsizing to smaller device Original DeviceNew DeviceCost Saving* XC2VP7XC2VP440% XC2VP20XC2VP750% XC2VP30XC2VP2054%

16 Adding Processor System to an FPGA Design - 4 - 17 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only UltraController Design Flow Place & Route Simulation HDL PPC405 PLB / Arbiter PLB EMC OPB GPIO OPB UART PLB2OPB Bridge OPB2PLB Bridge BRAM Block OPB / Arbiter JTAG CNTL PLB BRAM I/F ISE Download Bitstream ChipScope  Pro Hardware Verification EDK C Code GDB Software Debug Software Steps UltraController  HDL Module

17 Adding Processor System to an FPGA Design - 4 - 18 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Prepackaged Design UltraController  Instantiated in EDK UltraController  Instantiated in EDK

18 Adding Processor System to an FPGA Design - 4 - 19 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only UltraController Implementation Steps Add UltraController to HDL Design in ISE 1 Create Code in the Platform Studio - Leveraging Reference Examples - Simulate System Create Code in the Platform Studio - Leveraging Reference Examples - Simulate System 2 Download Design - Debug Download Design - Debug 3

19 Adding Processor System to an FPGA Design - 4 - 20 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Step 1: Add UC to the HDL in ISE

20 Adding Processor System to an FPGA Design - 4 - 21 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Step 2: Create the Code in EDK Write to LED Write to Sound Click to Compile SW

21 Adding Processor System to an FPGA Design - 4 - 22 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only System Simulate Behavioral and Structural Levels

22 Adding Processor System to an FPGA Design - 4 - 23 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Step 3: Download Using iMPACT

23 Adding Processor System to an FPGA Design - 4 - 24 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Outline ISE: Project Navigator Integration – Top Level – Submodule UltraController Case Study XPS: Xflow Integration

24 Adding Processor System to an FPGA Design - 4 - 25 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only EDK: Xflow Processor IP MPD Files system.ucf system.bit MHS File system.mhs PlatGen Xflow Hardware Data2MEM download.bit Compile Link Object Files Executable Libraries Source Code LibGen MSS File system.mss EDIF IP Netlists bram_init.bmm bram_init_bd.bmm Source Code Synthesis

25 Adding Processor System to an FPGA Design - 4 - 26 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Xflow Benefits to the user – Allows independent design of the processor system – Allows the designer to use one GUI to perform all design work Limitations – No direct control of synthesis and implementation options – No point-tool support

26 Adding Processor System to an FPGA Design - 4 - 27 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Xflow code directory –.c data directory –.ucf etc directory – bitgen.opt – bitgen.ut – download.cmd – fast_runtime.opt – BSDL files pcores directory – User IP – Customized BRAM controllers project_directorycode directorydata directoryetc directorypcores Required XPS Directory Structure synthesisTestApp [optional]

27 Adding Processor System to an FPGA Design - 4 - 28 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Controlling Xflow In the etc directory, there is a file called fast_runtime This is what it looks like: # Options for Translator # Type "ngdbuild -h" for a detailed list of ngdbuild command line options Program ngdbuild -p ; # Partname to use — picked from xflow commandline -nt timestamp; # NGO File generation. Regenerate only when # source netlist is newer than existing NGO file (default) -bm.bmm; # Block RAM memory map file ; # User design — pick from xflow command line.ngd; # Name of NGD file. Filebase same as design filebase End Program ngdbuild

28 Adding Processor System to an FPGA Design - 4 - 29 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Review Questions What are some of the advantages of using the ISE and XPS integration? What are some of the advantages of using the Xflow and XPS integration? How can UltraController  be beneficial?

29 Adding Processor System to an FPGA Design - 4 - 30 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Answers What are some of the advantages of using the ISE and XPS integration? – Allows you to add additional logic to the FPGA design – Allows you to synthesize the design by utilizing ISE supported synthesis tools – Allows you to control the FPGA Implementation flow by using ISE What are some of the advantages of using the Xflow and XPS integration? – Allows you to use one GUI to perform all design work How can UltraController  be beneficial? – Increases product functionality – Implementing the finite state machine in the PowerPC  improves logic efficiency – Reduces cost by downsizing

30 Adding Processor System to an FPGA Design - 4 - 31 © 2004 Xilinx, Inc. All Rights Reserved For Academic Use Only Where Can I Learn More? Tool documentation – Embedded System Tools Guide  Xilinx Platform Studio Support website – UltraController  Home Page — www.support.xilinx.com/ultracontroller – EDK Home Page: support.xilinx.com/edk

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