1. CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Bipolar transistors

2. PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier This leads to 1-directional current flow Forms junction capacitor –Capacitance highly voltage dependent –Can be nuisance or benefits

3. PN Junctions

4. Initial impurity concentration

5. PN Junctions

6. Depletion region widths: Barrier potential:

7. Example NA=10^15 atoms/cm^3, ND=10^16, vD=-10 Ni=2.25*10^20 Phi_o=26ln(10^15*10^16/2.25/10^20)=638 mV xp= - 3.5  m xn= 0.35  m Max field = q*NA*xp/  = -5.4*10^4 V/cm Note the large magnitude of the field

8. PN Junctions The depletion charge The junction capacitance

9. Realistic curve

10. Can be used as voltage controlled capacitor Here m = 1/2 for the step change in impurity concentration. For gradual concentration change, m = 1/3.

11. Impurity concentration profile for diffused pn junction

12. Current density at boundary due to wholes: Total : Diode current:

15. The MOS Transistor

17. TWO TYPES OF TRANSISTORS

18. Capacitors Two conductor plates separated by insulator for a capacitor Intentional capacitors vs parasitic capacitors Linear vs nonlinear capacitors Linear capacitors:

19. Integrated Capacitors in CMOS High density, good matching, but nonlinear

20. High density, good matching, good linearity, but require two-poly processes

21. Other Caps C gs of enhancement transistors metal to poly metal to metal PN junction –diffusion to substrate –side wall Fringe caps from top layer metals

22. Layering strategies

23. Parasitic Capacitors

25. Proper layout of capacitors For achieving C A = 2C B, which one is better?

26. Various Capacitor Errors

28. Resistors in CMOS Diffusion resistor polysilicon resistor well resistor metal layer resistor contact resistor

29. Diffusion resistor in n-well Is this resistor linear? Why?

30. Polysilicon resistor on FOX

31. n-well resistor on p-substrate

32. Bipolar in CMOS PNP

34. N+ P+ P contacts N-well P substrate PNP bipolar transistor in an N-well process Issues?

35. BJT in bipolar process In CMOS, the parasitics are worse

36. CMOS Transistors

37. Latch-up problem

38. Preventing Latch-up

40. ESD protection A very serious problem Not enough theoretical study Many trade secrets Learn from experienced designers