1. Constructive Computer Architecture Virtual Memory and Interrupts Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology November 13, 2015 http://csg.csail.mit.edu/6.175 L21-1

2. Address Translation: putting it all together Virtual Address TLB Lookup Page Table Walk Update TLB Page Fault (OS loads page) Protection Check Physical Address (to cache) miss hit the page is  memory  memory denied permitted Protection Fault hardware hardware or software software SEGFAULT Where? Resume the instruction November 13, 2015 http://csg.csail.mit.edu/6.175L21-2

3. Address Translation in Pipeline Machines Software handlers need a restartable exception on page fault or protection violation Handling a TLB miss needs a hardware or software mechanism to refill TLB Methods to overcome the additional latency of a TLB: slow down the clock pipeline the TLB and cache access virtual address caches parallel TLB/cache access PC Inst TLB Inst. Cache D Decode EM Data TLB Data Cache W + TLB miss? Page Fault? Protection violation? TLB miss? Page Fault? Protection violation?   November 13, 2015 http://csg.csail.mit.edu/6.175L21-3

4. Physical vs Virtual Address Caches? One cycle in case of a hit (+) cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) aliasing problems due to the sharing of pages (-) CPU Physical Cache TLB Primary Memory VA PA Alternative: place the cache before the TLB CPU VA (StrongARM) Virtual Cache PA TLB Primary Memory November 13, 2015 http://csg.csail.mit.edu/6.175L21-4

5. Aliasing in Virtual-Address Caches VA 1 VA 2 Page Table Data Pages PA VA 1 VA 2 1st Copy of Data at PA 2nd Copy of Data at PA TagData Two virtual pages share one physical page Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General Solution: Disallow aliases to coexist in cache Software (i.e., OS) solution for direct-mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in direct- mapped cache (early SPARCs) November 13, 2015 http://csg.csail.mit.edu/6.175L21-5

6. Concurrent Access to TLB & Cache Index L is available without consulting the TLB cache and TLB accesses can begin simultaneously Tag comparison is made after both accesses are completed Cases: L + b = kL + b < k L + b > k what happens here? VPN L b TLB Direct-map Cache 2 L blocks 2 b -byte block PPN Page Offset = hit? DataPhysical Tag Tag VA PA Virtual Index k Partially VA cache! November 13, 2015 http://csg.csail.mit.edu/6.175L21-6

7. Virtual-Index Physical-Tag Caches: Associative Organization VPN L = k-b b TLB Direct-map 2 L blocks PPN Page Offset = hit? Data Phy. Tag VA PA Virtual Index k Direct-map 2 L blocks = After the PPN is known, W physical tags are compared Allows cache size to be greater than 2 L+b bytes W ways November 13, 2015 http://csg.csail.mit.edu/6.175L21-7

8. Exception handling in a pipeline machine November 13, 2015L21-8 http://csg.csail.mit.edu/6.175

9. Exception Handling PC Inst. Mem D Decode EM Data Mem W + Illegal Opcode Overflow Data address Exceptions PC address Exception External Interrupts Ex D PC D Ex E PC E Ex M PC M Cause EPC Kill D Stage Kill F Stage Kill E Stage Select Handler PC Kill Writeback Commit Point 1. An instruction may cause multiple exceptions; which one should we process? 2. When multiple instructions are causing exceptions; which one should we process first? from the earliest stage from the oldest instruction November 13, 2015 http://csg.csail.mit.edu/6.175L21-9

10. Interrupt processing Internal interrupts can happen at any stage but cause a redirection only at Commit External interrupts are considered only at Commit If an instruction causes an interrupt then the external interrupt, if present, is given a priority and the instruction is executed again Some instructions, like Store, cannot be undone once launched. So an instruction is considered to have completed before an external interrupt is taken November 13, 2015 http://csg.csail.mit.edu/6.175L21-10

11. Exception Handling When instruction x in stage i raises an exception, its cause is recorded and passed down the pipeline For a given instruction, exceptions from the later stages of the pipeline do not override cause of exception from the earlier stages If an exception is present at commit: Cause and EPC registers are set, and pc is redirected to the handler PC Epoch mechanism takes care of redirecting the pc November 4, 2015 http://csg.csail.mit.edu/6.175L19-11

12. Killing vs Poisoning PC Inst Memory Decode Register File Execute Data Memory f2d Epoch m2c d2e Next Addr Pred scoreboard f12f2 e2m wrong path insts are dropped wrong path insts are poisoned This affects whether an instruction is removed from sb in case of an interrupt external interrupts considered at Commit November 4, 2015 http://csg.csail.mit.edu/6.175L19-12

13. Interrupt processing at Execute Incoming Interrupt -if (mem type) issue Ld/St -if (mispred) redirect -pass eInst to M stage -pass eInst to M stage unmodified no yes eInst will contain information about any newly detected interrupts at Execute November 13, 2015 http://csg.csail.mit.edu/6.175L21-13

14. Interrupt processing at Memory stage Incoming Interrupt -pass eInst with modified data to Commit -pass eInst to Commit unmodified no yes Memory Interrupt? noyes -pass new Cause to Commit November 13, 2015 http://csg.csail.mit.edu/6.175L21-14

15. Interrupt processing at Commit External Interrupt? EPC<= pc; causeR <= inCause; if (inCause after Reg Fetch) sb.rm; mode <= privilege; Redirect noyes Incoming interrupt no yes noyes -commit -sb.rm Incoming interrupt commit; sb.rm; EPC<= ppc; causeR <= Ext; mode <= privilege; Redirect EPC<= pc; causeR <= Ext; if (inCause after Reg Fetch) sb.rm; mode <= privilege; Redirect November 13, 2015 http://csg.csail.mit.edu/6.175L21-15

16. Final comment There is generally a lot of machinery associated with a plethora of exceptions in ISAs Precise exceptions are difficult to implement correctly in pipelined machines Performance is usually not the issue and therefore sometimes exceptions are implemented using microcode November 4, 2015 http://csg.csail.mit.edu/6.175L19-16 The code slides follow

17. One-Cycle SMIPS rule doExecute; let inst = iMem.req(pc); let dInst = decode(inst, csrf.getStatus); let rVal1 = rf.rd1(fromMaybe(?, dInst.src1)); let rVal2 = rf.rd2(fromMaybe(?, dInst.src2)); let eInst = exec(dInst, rVal1, rVal2, pc, ?); if(eInst.iType == Ld) eInst.data <- dMem.req(MemReq{op: Ld, addr: eInst.addr, data: ?}); else if(eInst.iType == St) let d <- dMem.req(MemReq{op: St, addr: eInst.addr, data: eInst.data}); if (isValid(eInst.dst)) rf.wr(fromMaybe(?, eInst.dst), eInst.data); … setting special registers … … next address calculation … endrule endmodule November 4, 2015 http://csg.csail.mit.edu/6.175L19-17

18. Type: Decoded Instruction typedef struct { IType iType; AluFunc aluFunc; BrFunc brFunc; Maybe#(RIndx) dst; Maybe#(RIndx) src1; Maybe#(RIndx) src2; Maybe#(Data) imm; Maybe#(CsrIndx) csr; } DecodedInst deriving(Bits, Eq); typedef enum {Unsupported, NoPermit, Alu, Ld, St, J, Jr, Br,..., Syscall, ERet} IType deriving(Bits, Eq); November 4, 2015 http://csg.csail.mit.edu/6.175L19-18

19. Decode function DecodedInst decode(Data inst, Status status); DecodedInst dInst = ?;... opSystem: begin case (funct3)... fnPRIV: begin // privilege inst dInst.iType = (case(inst[31:20]) fn12SCALL: Syscall; // sys call // ERET can only be executed under privilege mode fn12ERET: isPrivMode(status) ? Eret : NoPermit; default: Unsupported; endcase); dInst.dst = Invalid; dInst.src1 = Invalid; dInst.src2 = Invalid; dInst.imm = Invalid; dInst.aluFunc = ?; dInst.brFunc = NT; end... endcase end... return dInst; endfunction November 4, 2015 http://csg.csail.mit.edu/6.175L19-19

20. Set special registers if (eInst.iType==Syscall) begin csrf.setStatus(statusPushKU(csrf.getStatus)); csrf.setCause(32’h08); // cause for System call csrf.setEpc(pc); end else if (eInst.iType==ERet) begin cop.setStatus(statusPopKU(cop.getStatus)); end November 4, 2015 http://csg.csail.mit.edu/6.175L19-20

21. Redirecting PC if (eInst.iType==Syscall) pc <= csrf.getTvec; else if (eInst.iType==ERet) pc <= cop.getEpc; else pc <= eInst.brTaken ? eInst.addr : pc + 4; November 4, 2015 http://csg.csail.mit.edu/6.175L19-21