1. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 1 Digital Fundamentals CHAPTER 5 Combinational Logic Analysis

2. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 2 Basic Combinational Logic Circuits

3. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 3 Basic Combinational Logic Circuits AND-OR LogicAND-OR Logic AND-OR-Invert LogicAND-OR-Invert Logic Exclusive-OR LogicExclusive-OR Logic

4. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 4 Basic Combinational Logic Circuits AND-OR LogicAND-OR Logic

5. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 5 Basic Combinational Logic Circuits AND-OR Invert LogicAND-OR Invert Logic

6. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 6 Basic Combinational Logic Circuits Exclusive-OR LogicExclusive-OR Logic

7. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 7 Implementing Combinational Logic Implementing Combinational Logic

8. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 8 Implementing Combinational Logic Implementing Combinational Logic From Boolean expression to logic circuitFrom Boolean expression to logic circuit –Given a Boolean expression, create a logic circuit that implements that expression. From truth table to logic circuitFrom truth table to logic circuit –Given a truth table, create a logic circuit that implements that table.

9. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 9 The Universal Property of NAND and NOR Gates NAND and NOR gates are “universal” because they can used to produce any of the other logic functions.

10. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 10 The Universal Property of NAND Gates NAND Gate as an InverterNAND Gate as an Inverter

11. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 11 The Universal Property of NAND Gates Two NAND Gates as an AND GateTwo NAND Gates as an AND Gate

12. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 12 The Universal Property of NAND Gates Three NAND Gates as an OR GateThree NAND Gates as an OR Gate

13. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 13 The Universal Property of NAND Gates Four NAND Gates as OR GateFour NAND Gates as OR Gate

14. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 14 The Universal Property of NOR Gates NOR Gate as an InverterNOR Gate as an Inverter

15. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 15 The Universal Property of NOR Gates Two NOR Gates as an OR GateTwo NOR Gates as an OR Gate

16. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 16 The Universal Property of NOR Gates Three NOR Gates as an AND GateThree NOR Gates as an AND Gate

17. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 17 The Universal Property of NOR Gates Four NOR Gates as an AND GateFour NOR Gates as an AND Gate

18. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 18 Figure 5–19 Development of the AND-OR equivalent of the circuit in Figure 5–18. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

19. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 19 Figure 5–20 Illustration of the use of the appropriate dual symbols in a NAND logic diagram. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

20. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 20 Figure 5–21 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Example 5-9. Redraw using appropriate dual symbols.

21. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 21 Figure 5–22 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

22. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 22 NOR Logic – Negative AND A + B = A B NOR negative AND

23. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 23 Figure 5–24 NOR logic for X = (A + B)(C + D). Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. NOR Logic – Negative AND

24. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 24 Figure 5–25 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

25. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 25 Figure 5–26 Illustration of the use of the appropriate dual symbols in a NOR logic diagram. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

26. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 26 Figure 5–27 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Redraw using appropriate Dual symbols.

27. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 27 Figure 5–28 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

28. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 28 Figure 5–29 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

29. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 29 Figure 5–30 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Draw the timing diagram with the given inputs

30. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 30 Figure 5–42 Illustration of a node in a logic circuit. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Troubleshooting

31. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 31 Figure 5–43 Open output in driving gate. For simplicity, assume a HIGH is on one gate input. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

32. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 32 Figure 5–44 Open input in a load gate. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

33. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 33 Figure 5–45 Shorted output in the driving gate or shorted input in a load gate. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

34. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 34 Figure 5–46 Example of signal tracing and waveform analysis in a portion of a printed circuit board. TP indicates test point. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

35. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 35 Figure 5–47 Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Determine the fault in the circuit. Red line shows correct waveform. Green line is incorrect waveform.

36. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 36 VHDL V – VHSIC – Very High Speed Integrated CircuitV – VHSIC – Very High Speed Integrated Circuit HDL – Hardware Description LanguageHDL – Hardware Description Language Component name_of_component is port (port definitions); End component name_of_component

37. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 37 Figure 5–36 Predefined programs for a 2-input AND gate and a 2-input OR gate to be used as components in the data flow approach. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

38. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 38 Figure 5–40 A VHDL program for a combinational logic circuit after entry on a generic text editor screen that is part of a software development tool. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

39. Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 39 Figure 5–41 A typical waveform editor tool showing the simulated waveforms for the logic circuit described by the VHDL code in Figure 5–40. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.