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ECE-C302 Serial Addition – A Finite State Machine 1. Serial Parity Checker 2. Decimal Serial Adder 3. Radix r Serial Adder.

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Presentation on theme: "ECE-C302 Serial Addition – A Finite State Machine 1. Serial Parity Checker 2. Decimal Serial Adder 3. Radix r Serial Adder."— Presentation transcript:

1 ECE-C302 Serial Addition – A Finite State Machine 1. Serial Parity Checker 2. Decimal Serial Adder 3. Radix r Serial Adder

2 1. Serial Parity Checker Synchronous state machine (clock input ck) Synchronous state machine (clock input ck) States: even or odd number ones appeared at Port x since a reset (reset=‘1’) States: even or odd number ones appeared at Port x since a reset (reset=‘1’) z <= ‘0’ when even and ‘1’ when odd z <= ‘0’ when even and ‘1’ when odd x z ckreset evenodd X=‘0’ or reset=‘1’ X=‘1’ and reset=‘0’ X=‘0’ or reset=‘1’ X=‘1’

3 Hardware Description entity parity_checker is port(x, reset, ck: in std_logic; z: out std_logic); end parity_checker; Architecture behav of parity_checker is Architecture behav of parity_checker is Type state is (even, odd); Type state is (even, odd); Signal n_s : state; Signal n_s : state; Begin Begin Process(ck) Process(ck) Begin Begin If ck=‘1’ then If ck=‘1’ then Case n_s is Case n_s is When even => When even => Z <= ‘0’; Z <= ‘0’; If x=‘1’ and reset=‘0’ then n_s <= odd end if; If x=‘1’ and reset=‘0’ then n_s <= odd end if; …

4 Decimal Serial Adder Operand digits at Port a and b Operand digits at Port a and b Apply the operands starting from the least significant digits after a reset Apply the operands starting from the least significant digits after a reset State machine with two states State machine with two states a z ckreset No_carrycarry a+b<10 or reset=‘1’ a+b>9 and reset=‘0’ a+b<9 or reset=‘1’ a+b>8 b

5 Hardware Description entity decimal_serial_adder is port( a, b: in integer; reset, ck: in std_logic; z: out integer); end decimal_serial_adder; Architecture behav of decimal_serial_adder is Type state is (no_carry, carry); Type state is (no_carry, carry); Signal n_s : state; Signal n_s : state; Begin Begin Process(ck) Process(ck) Begin Begin If ck=‘1’ then If ck=‘1’ then Case n_s is Case n_s is When no_carry => When no_carry => Z <= a+b mod 10; Z <= a+b mod 10; If n_s <= no_carry; If a+b<10 or reset=‘1’ n_s <= no_carry; elsif ; elsif a+b>9 and reset=‘0’ then n_s <= carry; else null; else null; …

6 Code for Synthesis Package dec_pack is subtype dec_integer is integer range (0 to 9); End dec_pack; -- use work.dec_pack.all entity decimal_serial_adder is port( a, b: in dec_integer; reset, ck: in std_logic; z: out dec_integer); end decimal_serial_adder; Architecture behav_synth of decimal_serial_adder is Type state is (no_carry, carry); Type state is (no_carry, carry); Signal n_s : state; Signal n_s : state; Begin Begin Process(ck) Process(ck) subtype my_integer: integer range(0 to 18); variable temp: my_integer; Begin Begin If ck=‘1’ then If ck=‘1’ then Case n_s is Case n_s is When no_carry => When no_carry => temp := a+b; temp := a+b; If temp n_s<=no_carry; z<=temp; If temp<10 or reset=‘1’ n_s<=no_carry; z<=temp; elsif temp; elsif temp>9 and reset=‘0’ then n_s<=carry; z<=temp-10; else null; else null; …

7 Radix-r Serial Adder Operand radix-r unsigned at Port a and b Operand radix-r unsigned at Port a and b –For example, when r = 2 we have binary adder –When r = 16 we have hexadecimal adder B + F = 1A (B=11, F=15, 11+15=26 and 26-16=10=A) B + F = 1A (B=11, F=15, 11+15=26 and 26-16=10=A) a z ckreset No_carrycarry a+b<r or reset=‘1’ a+b>r-1 and reset=‘0’ a+b<r-1 or reset=‘1’ a+b>r-2 b

8 Code for Synthesis Package radixr_pack is subtype radixr_integer is integer range (0 to r-1); End radixr_pack; use work.dec_pack.all; entity radixr_serial_adder is Generic r: natural := 2; port( a, b: in radixr_integer; reset, ck: in std_logic; z: out radixr_integer); z: out radixr_integer); end radixr_serial_adder; Architecture behav_synth of radixr_serial_adder is Type state is (no_carry, carry); Type state is (no_carry, carry); Signal n_s : state; Signal n_s : state; Begin Begin Process(ck) Process(ck) subtype my_integer is integer range(0 to 2*(r -1)); variable temp: my_integer; Begin Begin If ck=‘1’ then If ck=‘1’ then Case n_s is Case n_s is When no_carry => When no_carry => temp := a+b; temp := a+b; If temp n_s<=no_carry; z<=temp; If temp<r or reset=‘1’ n_s<=no_carry; z<=temp; elsif temp; elsif temp>r-1 and reset=‘0’ then n_s<=carry; z<=temp-r; else null; else null; …

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