1. 1 COMP541 Combinational Logic - 3 Montek Singh Jan 23, 2012

2. Today’s Topics 2  Quick tips on Lab #1  Other type of gates XOR, XNOR XOR, XNOR compound gates compound gates transmission gates transmission gates  Non-Boolean values “Don’t Cares”, or X values “Don’t Cares”, or X values “Floating values”, or Z values “Floating values”, or Z values

3. 3 Lab #1 tips  Testing your circuit using a Verilog test fixture  Module module lab1_part1( module lab1_part1( input A, B, Cin, output Sum);  Ports referenced as lab1_part1 uut(X, Y, Z, T) lab1_part1 uut(X, Y, Z, T)  Also as lab1_part1 uut(.A(X),.B(Y),.Sum(T),.Cin(Z)) lab1_part1 uut(.A(X),.B(Y),.Sum(T),.Cin(Z)) Circuit to be tested (“uut”) Stimulus: initial begin … end inputs outputs Verilog test fixture

4. Other Types of Gates 4

5. Exclusive OR 5  Exclusive OR  What lay people mean by “or”  Symbol is  Plus in a circle Plus in a circle

6. Parity Function 6  Recall how parity works Ask class Ask class  Write truth table for two input even parity What needs to be generated for parity bit? What needs to be generated for parity bit?  What function of two inputs gives you this?

7. XOR Gives Odd Function 7  As many inputs as necessary  How do you get odd parity?  Design even parity generator for 3-bit signal Draw with XOR, then sum-of-products w/ NAND gates Draw with XOR, then sum-of-products w/ NAND gates  How do you design a parity detector?

8. Others 8

9. CMOS Transmission Gates 9  Act like electronic switches

10. XOR using Transmission Gate 10

11. Introduction to Circuits 11

12. Introduction to Circuits 12  A logic circuit is composed of: Inputs Inputs Outputs Outputs Functional specification Functional specification Timing specification Timing specification

13. Circuits  Nodes Inputs: A, B, C Inputs: A, B, C Outputs: Y, Z Outputs: Y, Z Internal: n1 Internal: n1  Circuit elements E1, E2, E3 E1, E2, E3 Each a circuit Each a circuit 13

14. Types of Logic Circuits  Combinational Logic Memoryless Memoryless Outputs determined by current values of inputs Outputs determined by current values of inputs  Sequential Logic Has memory Has memory Outputs determined by previous and current values of inputs Outputs determined by previous and current values of inputs 14

15. Rules of Combinational Composition Composition rules: Every circuit element is itself combinational Every circuit element is itself combinational Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element  no output shorts The circuit contains no cyclic paths The circuit contains no cyclic paths  every path through the circuit visits each circuit node at most once (latches are made via a cyclic path) Example: Example: 15

16. Aside: Circuit Schematics with Style 16 Drawing style/conventions: (where possible) Inputs are on the left (or top) side of a schematic Inputs are on the left (or top) side of a schematic Outputs are on the right (or bottom) side of a schematic Outputs are on the right (or bottom) side of a schematic Gates should flow from left to right Gates should flow from left to right Straight wires are better to use than jagged wires Straight wires are better to use than jagged wires

17. Circuit Schematic Rules (cont.) Wire connections A dot where wires cross indicates a connection A dot where wires cross indicates a connection Wires crossing without a dot make no connection Wires crossing without a dot make no connection Wires always connect at a T junction Wires always connect at a T junction 17

18. Multiple Output Circuits Output asserted corresponding to most significant TRUE input 18

19. Example: Priority Encoder Hardware 19

20. Values that are not 0’s and 1’s Don’t Cares (X) Floating values (Z) 20

21. Don’t Cares (X) 21

22. Actually: Several Meanings of X 22  Don’t care  Contention (illegal input value)  Uninitialized value In a simulator In a simulator

23. Floating: Z  Floating, high impedance, open, high Z Floating output might be 0, 1, or somewhere in between Floating output might be 0, 1, or somewhere in between A voltmeter won’t indicate whether a node is floating A voltmeter won’t indicate whether a node is floating Allows connecting outputs Allows connecting outputs Tristate Buffer 23

24. Next  Wed: Full Tutorial on Verilog so you are more ready for Lab #2 so you are more ready for Lab #2  Mon next week: Combinational building blocks Combinational building blocks 24