1. Compton Trigger Design Update Tanja Horn Compton Working Group 6 June 2008

2. 96 inputs with 32 outputs CAEN Module V1495 Commercially available General purpose VME board Can be directly customized by the user Field Programmable Gate Arrays (FPGA)

3. Background Fall 2007 – Hall B IC trigger design (B. Raydo, S. Boyarinov) Jan-March 2008 – Compton working group meeting. Trigger concept for Compton DAQ based on the existing Hall B design proposed (TH) March-May 2008 – Development and implementation of Hall B trigger using similar technology (V. Kubarovsky et al.) June 2008 – development of firmware for Compton DAQ could begin

4. Design Criteria Four detector planes, 96 microstrips/plane Expected rate is 100 kHz on average Form trigger within 500ns Trigger efficiency is not critical Background suppression important

5. Design Concept Design based on: Modern hardware Existing software and firmware Cluster finding algorithm being developed by S. Boyarinov Flexibility of the design lies in the upgradability of the firmware Functionality can be added without additional hardware Incremental development possible

6. Proposed Compton Trigger Layout Master Trigger Board Plane Trigger Boards Both stages of the trigger (plane and master) require different firmware Discriminator, 16 chan ?

7. Design Implementation Stage 1: Testing and Initial Operations Plane firmware: OR of all strips Master firmware: any logic through 4:1 lookup table (8:1 implemented) Stage 2: Regular Operations Plane firmware: linear cluster finding, multi cluster rejection Master firmware: cluster readout through master (input through ECL)?, 8:1 lookup table (trigger, veto), digital oscilloscope Additional features: Graphical User Interface based on Hall B design Stage 3: Future Development Plane firmware: Master firmware: background suppression through simple tracking?

8. ModelSIM-Altera Simulation needed to validate the design Code example from Ben

9. Rate Test (6/5/08): D16 CPU single cycle/DMA single cycle Figure from Ben Transaction time: 1.2 μs Readout rate: ~2 Mb/s

10. Figure from Ben Rate Test (6/5/08): D16 CPU block transfer/DMA single cycle Transaction time: 0.43 μs Readout rate: 4.7 Mb/s