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1 Contents Reviewed Rabaey CH 3, 4, and 6
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2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_2.jpg "2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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3 The PMOS Transistor [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![3 The PMOS Transistor [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_3.jpg "3 The PMOS Transistor [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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4 The CMOS Technology [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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5 Threshold Voltage Concept [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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6 Current-Voltage Relations [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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7 Transistor in Saturation [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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8 2-D Representation of MOS Transistor [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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9 Switch-Level View of NMOS & PMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![9 Switch-Level View of NMOS & PMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_9.jpg "9 Switch-Level View of NMOS & PMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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10 CMOS Switch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![10 CMOS Switch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_10.jpg "10 CMOS Switch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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11 CMOS Inverter [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![11 CMOS Inverter [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_11.jpg "11 CMOS Inverter [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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12 CMOS Inverter Layout Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2 m =2 [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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13 NMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![13 NMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_13.jpg "13 NMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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14 PMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![14 PMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_14.jpg "14 PMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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15 Switches in Parallel [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![15 Switches in Parallel [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_15.jpg "15 Switches in Parallel [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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16 2-Input CMOS NAND Gate: the Switch View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![16 2-Input CMOS NAND Gate: the Switch View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_16.jpg "16 2-Input CMOS NAND Gate: the Switch View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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17 2-Input CMOS NAND Gate: the Circuit View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![17 2-Input CMOS NAND Gate: the Circuit View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_17.jpg "17 2-Input CMOS NAND Gate: the Circuit View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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18 N-input CMOS NAND Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![18 N-input CMOS NAND Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_18.jpg "18 N-input CMOS NAND Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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19 4-Input NAND Gate In1In2In3In4 Vdd GND Out [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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20 2-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![20 2-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_20.jpg "20 2-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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21 N-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![21 N-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_21.jpg "21 N-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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22 Properties of CMOS Gates Vdd and GND are never directly connected i.e. no shorting Output is always connected to either Vdd or GND i.e. it never floats
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23 Making Compound Gates in CMOS F = ((A.B) + (C.D)) [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![23 Making Compound Gates in CMOS F = ((A.B) + (C.D)) [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_23.jpg "23 Making Compound Gates in CMOS F = ((A.B) + (C.D)) [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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24 Key Idea in CMOS Compound Logic Gates [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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25 More on CMOS Logic Style [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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26 Pull-Up and Pull-Down Circuits [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![26 Pull-Up and Pull-Down Circuits [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_26.jpg "26 Pull-Up and Pull-Down Circuits [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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27 CMOS Compound Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![27 CMOS Compound Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_27.jpg "27 CMOS Compound Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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28 What is this? [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![28 What is this [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_28.jpg "28 What is this [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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29 How do we implement these? Z = (A.B.C.D)’ Z = ((A.B) + C.(A+B))’ Z = A.B + A’.B’ what is this? Z = A.B’.C’ + A’.B’.C + A’.C’.B + A.B.C what is this?
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30 A 2-Input CMOS Multiplexer Output = A.S + B.S’ [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![30 A 2-Input CMOS Multiplexer Output = A.S + B.S’ [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_30.jpg "30 A 2-Input CMOS Multiplexer Output = A.S + B.S’ [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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31 How can one implement multiplexer using CMOS gates?
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32 Layout: the Standard Cell Approach [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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33 Two versions of a.(b+c) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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34 Logic Graph [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
![34 Logic Graph [Adapted from Copyright 1996 UCB]](http://images.slideplayer.com./27/9049214/slides/slide_34.jpg "34 Logic Graph [Adapted from Copyright 1996 UCB]")
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35 Consistent Euler Path [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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36 Example: x = ab + cd [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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37 Existence of Consistent Euler Paths May depend on the way the Boolean expression is written Example: x = (A + B.C + D.E)’ has no consistent Euler paths But, x = (B.C + A + D.E)’ does
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38 Memory & Storage in CMOS
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39 A CMOS Positive Level- Sensitive D Latch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![39 A CMOS Positive Level- Sensitive D Latch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com./27/9049214/slides/slide_39.jpg "39 A CMOS Positive Level- Sensitive D Latch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
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40 A CMOS Positive Edge- Triggered D Register
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41 Performance Analysis of CMOS Gates
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42 MOS Transistors are not “ Ideal ” Switches [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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43 CMOS Inverter: A More Detailed View [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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44 CMOS Inverter: Steady State Response [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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45 CMOS Inverter: Transient Response [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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46 What is the value of R on ? [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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47 Numerical Examples for 1.2 m CMOS [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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48 Transistor Sizing [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
![48 Transistor Sizing [Adapted from Copyright 1996 UCB]](http://images.slideplayer.com./27/9049214/slides/slide_48.jpg "48 Transistor Sizing [Adapted from Copyright 1996 UCB]")
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49 Propagation Delay Analysis [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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50 Analysis of Propagation Delay [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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51 Design for Worst Case [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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52 Influence of Fan-in and Fan-out on Delay [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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53 t p as a Function of Fan-in [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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54 Fast Complex Gates - I [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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55 Fast Complex gates - II [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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56 Fast Complex Gates - III [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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57 Fast Complex Gates - IV [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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58 Example: Full Adder [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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59 Revised Full Adder [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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