1. Trigger System Status Adele Di Cicco

2. 86.4 cm28.8 cm 9.6 cm T600 pixel definition

3. Trigger System Adele Di Cicco Napoli 4 Febbraio 2004

4. LTCU

5. Main technical specification

6. Trigger definitions TCU gives Global trigger when a MAJORITY condition is met in PMT logic. PMT logic. AWS logic. AWS logic. TCU gives Local Trigger according to data recorded during drift time.

7. GLOBAL/LOCAL trigger BUSY logic After a trigger request TS gives the DRIFT signal to all v789 boards During a DRIFT, TCU doesn’t accept any other trigger request and decides globality/locality of event. After the DRIFT time, TS according to topology of event gives global trigger to all crate or local trigger to fired crates. during a GLOBAL_BUSY (DAQ dead time for acquisition data download from all chambers) it accepts only a Local Trigger request

8. Flow Chart PMT Trigger condition logic Global trigger request Local trigger request Global drift or busy? Acquire all crates No trigger Acquire only fired pixels Local drift or busy? PMT-pixels coincidences logic Pixels Majority/Pattern logic PMT local trigger request? Wire planes coincidence Logic (pixel fired) No Trigger request AWS Discriminator LTCU - PMTAWS - LTCU Discriminator TCU TS PMT

9. Rack 11Rack 13 Each 100  s TCU makes pictures of detector Window runs on the detector Majority condition is checked for each window If majority condition (>1) is verified,horizontal scanning will start. General Idea on Partial majority

10. Spot detection Freeze detector It Sums pixels in the stripe and it stores pixels in shift register Majority Condition is verified? It Sums two adjacent stripes ACC=0 Start horizontal scanning It sums two adjacent pixels Sum equal 0? ACC=ACC+RowSum ACC equal Total pix end ACC=0 end

11. ADDR[4:0] SYNC BLK AND BLK 9 INA INB MASK 9 9 AA BB 13 A0_B[4:0] A1_B[5:1] A2_B[6:2] A3_B[7:3] A4_B[8:4] A5_B[9:5] A6_B[10:6] A7_B[11:7] A8_B[12:8] FLASH ENC REG A 1 ADDRESSGENERATOR FLASH CLK PIPELINE SYNC BLK 5 5 Central Unit REG B 13 SUM REG ACC PISO BLK

12. Pixel detection (using only two coordinates) 3s3s IND2 IND2 streched Collection Pixel

13. 3s3s A1 A2 3s3s B1B2 A1 A2 B1 3s3s A1 A1 delayed A2 delayed B1

14. Internal memory 0 #0 N° Fired Pixel Stop Address N° Spot N° isolated pixel #1 N° Fired Pixel Stop Address N° isolated pixel N° Spot #0 N° Fired Pixel Stop Address N° Spot N° isolated pixel #1 N° Fired Pixel Stop Address N° isolated pixel N° Spot #0 N° Fired Pixel Stop Address N° Spot N° isolated pixel #1 N° Fired Pixel Stop Address N° isolated pixel N° Spot #0 N° Fired Pixel Stop Address N° Spot N° isolated pixel #1 N° Fired Pixel Stop Address N° isolated pixel N° Spot FPGA

15. TCU 20 boards Board18 Board 2 Board 1 FIFO FPGA Analog circuit Board18 Board 2 Board 1 FIFO FPGA Analog circuit Board18 Board 2 Board 1 FIFO FPGA Analog circuit Board18 Board 2 Board 1 FIFO FPGA Analog circuit

16. Status of all system LTCU prototype is finished and tested in the SER  Tests on DAQ are going on these days (Pietro,Paolo,Adele).  The board’s documentation has been done (Adele,Maurizio).  Test will be finished at the end of February  Test at the CERN will be start on beginning of March (Adele) TCU block scheme definition is in progress  New scheme can be proposed